PCI Power Management

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The integrated GbE controller supports the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power Management (APM). This enables the network-related activity (using an internal host wake signal) to wake up the host. For example, from S3 and S4 to S0.

The integrated GbE controller contains power management registers for PCI and supports D0 and D3 states. PCI transactions are only allowed in the D0 state, except for host accesses to the integrated GbE controller’s PCI configuration registers.

Note:Refer to SLP_LAN# Pin Behavior.

The PCH controls the voltage rails into the external LAN PHY using the SLP_LAN# pin.

The LAN PHY is always powered when the Host and Intel^® CSME systems are running.
- SLP_LAN#=’1’ whenever SLP_S3#=’1’ or SLP_A#=’1’.

If the LAN PHY is required by Intel^® CSME in Sx/M-Off , Intel^® CSME must configure SLP_LAN#=’1’ irrespective of the power source and the destination power state. Intel^® CSME must be powered at least once after G3 to configure this.

If the LAN PHY is required after a G3 transition, the host BIOS must set AG3_PP_EN.

If the LAN PHY is required in Sx/M-Off, the host BIOS must set SX_PP_EN.

If the LAN PHY is not required if the source of power is battery, the host BIOS must set DC_PP_DIS.

Host System Management Bus (SMBus) Controller

Ethernet Interface Host System Management Bus (SMBus) Controller