Power Plane Control

The SLP_​S3# output signal can be used to cut power to the system core supply, since it only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power must be maintained to the PCH primary well, and to any other circuits that need to generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM) all signals attached to powered down planes will be tri-stated or driven low, unless they are pulled using a Pull-up resistor.

Cutting power to the system core supply may be done using the power supply or by external FETs on the motherboard.

The SLP_​S4# or SLP_​S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard.

The SLP_​S4# output signal is used to remove power to additional subsystems that are powered during SLP_​S3#, (moved from SLP_​S5# description to SLP_​S4#) as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard.

SLP_​S5# output signal can be used to cut power to the system core supply. (moved to SLP_​S4# description --- as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard.)

SLP_​A# output signal can be used to cut power to the Intel^® Converged Security and Management Engine and SPI flash on a platform that supports the M3 state (for example, certain power policies in Intel^® AMT).

SLP_​LAN# output signal can be used to cut power to the external Intel^® GbE PHY device.

SLP_​S4# and Suspend-to-RAM Sequencing

The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_​S4# signal should be used to remove power to system memory rather than the SLP_​S5# signal. The SLP_​S4# logic in the PCH provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time.

PCH_​PWROK Signal

When asserted, PCH_​PWROK is an indication to the PCH that its core well power rails are powered and stable. PCH_​PWROK can be driven asynchronously. When PCH_​PWROK is low, the PCH asynchronously asserts PLTRST#. PCH_​PWROK must not glitch, even if PCH_​RSMRST# is low.

It is required that the power associated with PCIe* have been valid for 99 ms prior to PCH_​PWROK assertion in order to comply with the 100 ms PCIe* 2.0 specification on PLTRST# de-assertion.

BATLOW# (Battery Low)

The BATLOW# input can inhibit waking from S4, S5 and Deep Sx states if there is not sufficient power. It also causes an SMI if the system is already in an S0 state.

SLP_​LAN# Pin Behavior

The PCH controls the voltage rails into the external LAN PHY using the SLP_​LAN# pin.

• The LAN PHY is always powered when the Host and Intel^® CSME systems are running.
  • SLP_​LAN#=’1’ whenever SLP_​S3#=’1’ or SLP_​A#=’1’.
• If the LAN PHY is required by Intel^® CSME in Sx/M-Off or Deep Sx, Intel^® CSME must configure SLP_​LAN#=’1’ irrespective of the power source and the destination power state. Intel^® CSME must be powered at least once after G3 to configure this.
• If the LAN PHY is required after a G3 transition, the host BIOS must set AG3_​PP_​EN.
• If the LAN PHY is required in Sx/M-Off, the host BIOS must set SX_​PP_​EN.
• If the LAN PHY is required in Deep Sx, the host BIOS must keep DSX_​PP_​DIS cleared.
• If the LAN PHY is not required if the source of power is battery, the host BIOS must set DC_​PP_​DIS.

The flow chart below shows how a decision is made to drive SLP_​LAN# every time its policy needs to be evaluated.

SLP_​WLAN# Pin Behavior

The PCH controls the voltage rails into the external wireless LAN PHY using the SLP_​WLAN# pin.

• The wireless LAN PHY is always powered when the Host is running.
  • SLP_​WLAN#=’1’ whenever SLP_​S3#=’1’.
• If Wake on Wireless LAN (WoWLAN) is required from S4/S5 states, the host BIOS must set HOST_​WLAN_​PP_​EN.
• If WoWLAN is required from Deep Sx, the host BIOS must set DSX_​WLAN_​PP_​EN.
• If Intel^® CSME has access to the Wireless LAN device:
  • The Wireless LAN device must always be powered as long as Intel^® CSME is powered. SLP_​WLAN#=’1’ whenever SLP_​A#=’1’.
  • If Wake on Wireless LAN (WoWLAN) is required from M-Off state, Intel^® CSME will configure SLP_​WLAN#=’1’ in Sx/M-Off.

Intel^® CSME configuration of SLP_​WLAN# in Sx/M-Off is dependent on Intel^® CSME power policy configuration.

When the Wireless LAN device is an integrated connectivity device (CNVi) the power to the CNVi external RF chip (CRF) must be always on. In this case the SLP_​WLAN# shall not control the CRF 3.3 V power rail.

PRIMPWRDNACK Steady State Pin Behavior

Below table summarizes PRIMPWRDNACK pin behavior.

RTCRST# and SRTCRST#

RTCRST# is used to reset PCH registers in the RTC Well to their default value. If a jumper is used on this pin, it should only be pulled low when system is in the G3 state and then replaced to the default jumper position. Upon booting, BIOS should recognize that RTCRST# was asserted and clear internal PCH registers accordingly. It is imperative that this signal not be pulled low in the S0 to S5 states.

SRTCRST# is used to reset portions of the Intel^® Converged Security and Management Engine and should not be connected to a jumper or button on the platform. The only time this signal gets asserted (driven low in combination with RTCRST#) should be when the coin cell battery is removed or not installed and the platform is in the G3 state. Pulling this signal low independently (without RTCRST# also being driven low) may cause the platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that SRTCRST# not be pulled low in the S0 to S5 states.