I/O Signal Planes and States

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Revision History
Introduction
PCH Controller Device IDs
- Revision IDs
- Device IDs
Memory Mapping
- Functional Description
- Memory Map
Audio Voice and Speech
Ballout Definition
Connectivity Integrated (CNVi)
Controller Link
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Direct Media Interface (DMI)
Enhanced Serial Peripheral Interface (eSPI)
Gigabit Ethernet Controller
Host System Management Bus (SMBus) Controller
Integrated Sensor Hub (ISH)
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers
PCI Express* (PCIe*)
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Serial ATA (SATA)
Serial Peripheral Interface (SPI)
System Clocks
- Integrated Clock Controller (ICC)
  - Signal Descriptions
- I/O Signal Pin States
System Management Interface and SMLink
Touch Host Controller (THC)
Universal Serial Bus (USB)
General Purpose Input and Output
- Functional Description
- Signal Description
GPIO Serial Expander
Private Configuration Space Port ID
Security Firmware Engines
- Intel® Converged Security and Management Engine (Intel® CSME)
- Intel® Silicon Security Engine
System Management
- Theory of Operation
  - TCO Modes
Testability and Monitoring
- Signal Description
- I/O Signal Planes and States
Miscellaneous Signals
Processor Sideband Signals
- Signal Description
- I/O Signal Planes and States
Power Delivery
- Power and Ground Signals
Power Management
Thermal Sensor
Electrical Characteristics

Signal Name	Power Plane	During Reset³	Immediately after Reset³	S4/S5
SATA_[0:7]_TXN SATA_[0:7]_TXP SATA_[0:7]_RXN SATA_[0:7]_RXP	Primary	Internal Pull-down	Internal Pull-down	Internal Pull-down
SATALED#	Primary	Undriven	Undriven	Undriven
SATA_DEVSLP[0:7]¹	Primary	Undriven	Undriven	Undriven
SATAGP[0:7]²	Primary	Undriven	Undriven	Undriven
SATAXPCIE[0:7]²	Primary	Internal Pull-up	Internal Pull-up	Undriven
SATA_SDATAOUT[0:1]	Primary	Undriven	Undriven	Undriven
SATA_SLOAD	Primary	Undriven	Undriven	Undriven
SATA_SCLOCK	Primary	Undriven	Undriven	Undriven
Notes: Pin defaults to GPIO mode. The pin state during and immediately after reset follows default GPIO mode pin state. The pin state for S0 to S4/S5 reflects assumption that GPIO Use Select register was programmed to native mode functionality. If the GPIO Use Select register is programmed to GPIO mode, refer to Intel® 800 Series Chipset Family PCH - GPIO implementation summary for the pin state during reset and pin state immediately after reset. Pin defaults to Native mode as SATAXPCIEx depends on soft-strap. Reset reference for primary well pins is PCH_RSMRST#.

Serial Peripheral Interface (SPI)

Integrated Pull-Ups and Pull-Downs Serial Peripheral Interface (SPI)