Fixed I/O Address Ranges
The following table shows the Fixed I/O decode ranges from the processor perspective. For each I/O range, there may be separate behavior for reads and writes.
I/O cycles that go to target ranges that are marked as Reserved will be handled as follows:
Writes are ignored and reads will return all 1's. The P2SB will claim many of the fixed I/O accesses and forward those transactions over IOSF-SB to their functional target.
Address ranges that are not listed or marked Reserved are NOT positively decoded (unless assigned to one of the variable ranges) and will be internally terminated.
Fixed I/O Ranges Decoded by PCH
| I/O Address | Read Target | Write Target | Internal Unit (Unless[E]: External)2 | Separate Enable/Disable |
|---|
| 2E-2F | Super I/O | Super I/O | [E] Forwarded to eSPI | Yes. ESPI_IOD_IOE.SE |
| 4E-4F | Microcontroller | Microcontroller | [E] Forwarded to eSPI | Yes. ESPI_IOD_IOE.ME2 |
| 60h | Keyboard Controller | Keyboard Controller | [E] Forwarded to eSPI | Yes, with 64h. ESPI_IOD_IOE.KE |
| 62h | Microcontroller | Microcontroller | [E] Forwarded to eSPI | Yes, with 66h. ESPI_IOD_IOE.ME1 |
| 64h | Keyboard Controller | Keyboard Controller | [E] Forwarded to eSPI | Yes, with 60h. ESPI_IOD_IOE.KE |
| 66h | Microcontroller | Microcontroller | [E] Forwarded to eSPI | Yes, with 62h. ESPI_IOD_IOE.ME1 |
| 70h | RTC Controller | NMI and RTC Controller | RTC | None |
| 71h | RTC Controller | RTC Controller | RTC | None |
| 72h | RTC Controller | RTC Controller | RTC | None. Alias to 70h if RC.UE4=0, else 72h |
| 73h | RTC Controller | RTC Controller | RTC | None. Alias to 71h if RC.UE=’0’, else 73h |
| 74h | RTC Controller | RTC Controller | RTC | None |
| 75h | RTC Controller | RTC Controller | RTC | None |
| 76h-77h | RTC Controller | RTC Controller | RTC | None. Alias to 70h-71h if RC.UE=0, else 76h-77h |
| 80h3 | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. eSPI if GCS.RPR=’0’ |
| 84h - 86h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. eSPI if GCS.RPR=’0’ |
| 88h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. eSPI if GCS.RPR=’0’ |
| 8Ch - 8Eh | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. eSPI if GCS.RPR=’0’ |
| 90h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 80h |
| 94h - 96h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 8xh |
| 98h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 88h |
| 9Ch - 9Eh | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 8xh |
| 200-207h | Gameport Low | Gameport Low | Forwarded to eSPI | Yes. ESPI_CS1IORE.LGE |
| 208-20Fh | Gameport High | Gameport High | Forwarded to eSPI | Yes ESPI_CS1IORE.HGRE |
- Only if the Port 61 Alias Enable bit (GIC.P61AE) bit is set. Otherwise, the cycle is internally terminated by the PCH.
- Destination of eSPI when eSPI Disabled pin strap is 0.
- This includes byte, word or double-word (DW) access at I/O address 80h.
- Read to Port 70 will read from RTC in PCH-S. Write to Port 70h will generate a write to ITSS (in SOC-S), and a write to RTC (in PCH-S).
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