Protocols

Below is an overview of the basic eSPI protocol. Refer to the latest eSPI Specification and corresponding platform eSPI Compatibility Specification for more details (Refer to Table: References).

An eSPI transaction consists of a Command phase driven by the host, a turn-around phase (TAR), and a Response phase driven by the device.

A transaction is initiated by the Processor/PCH through the assertion of CS#, starting the clock and driving the command onto the data bus. The clock remains toggling until the complete response phase has been received from the device.

The serial clock must be low at the assertion edge of the CS# while ESPI_​RESET# has been de-asserted. The first data is driven out from the processor while the serial clock is still low and sampled on the rising edge of the clock by the device. Subsequent data is driven on the falling edge of the clock from the processor and sampled on the rising edge of the clock by the device. Data from the device is driven out on the falling edge of the clock and is sampled on a falling edge of the clock by the processor/PCH.

All transactions on eSPI are in multiple of 8 bits (one byte).