System Power States, Advanced Configuration and Power Interface (ACPI)

Intel® 800 Series Chipset Family Platform Controller Hub (PCH)

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
833778	02/06/2025		Public

This section describes System Power States and ACPI states supported by the PCH.

General System Power States

State		Description
G0/S0/C0		Full On: Processor operating. Individual devices may be shut to save power. The different Processor operating levels are defined by Cx states.
GO/S0/Cx		Cx state: Processor manages C-states by itself and can be in low power state
G1/S3		Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut to non-critical circuits. Memory is retained, and refreshes continue. All external clocks are shut off; RTC clock and internal ring oscillator clocks are still toggling. In S3, SLP_S3 signal stays asserted, SLP_S4 and SLP_S5 are inactive until a wake occurs.
G1/S4		Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut to the system except to the logic required to resume. Externally appears same as S5 but may have different wake events. In S4, SLP_S3 and SLP_S4 both stay asserted and SLP_S5 is inactive until a wake occurs. In S4, SLP_S4 would stay asserted and SLP_S5 is inactive until a wake occurs
G2/S5		Soft Off: System context not maintained. All power is shut except for the logic required to restart. A full boot is required when waking. Here, SLP_S3, SLP_S4, and SLP_S5 are all active until a wake occurs. Here, SLP_S4, and SLP_S5 are all active until a wake occurs.
G3		Mechanical OFF: System context not maintained. All power shut except for the RTC. No “Wake” events are possible because the system does not have any power. This state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the “waking” logic. When system power returns the transition will depend on the state just prior to the entry to G3.

The table below shows the transitions rules among the various states.

Note:Transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S5, it may appear to pass through the G1/S4 state. These intermediate transitions and states are not listed in the table below.

State Transition Rules for the PCH

Present State	Transition Trigger	Next State
G0/S0/C0	SLP_EN bit set Power Button Override³ Mechanical Off/Power Failure	G0/S0/Cx G1/S4, or G2/S5 state G2/S5 G3
G0/S0/Cx	Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0 S5 G3
G1/S3	Any Enabled Wake Event Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0² G2/S5 G3
G1/S4	Any Enabled Wake Event Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0² G2/S5 G3
G2/S5	Any Enabled Wake Event Mechanical Off/Power Failure	G0/S0/C0² G3
G2	Any Enabled Wake Event Mechanical Off/Power Failure Power Button Override	G0/S0/C0² G1/S4 or G2/S5 G3 G2/S5
G3	Power Returns	S0/C0 (reboot) or G2/S5⁴ (stay off until power button pressed or other wake event)^1,2
Notes: Some wake events can be preserved through power failure. Transitions from the S4-S5 states to the S0 state are deferred until BATLOW# is inactive. Includes all other applicable types of events that force the host into and stay in G2/S5. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4.

System Power Planes

The system has several independent power planes, as described in the table below.

Note:When a particular power plane is shut off, it should go to a 0 V level.

System Power Plane

Plane	Controlled By	Description
Processor	SLP_S3# signal	The SLP_S3# signal can be used to cut the power to the processor completely.
Main (Applicable to Platform)	SLP_S3# signal	When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system The PCH PCI Express* will typically be power-gated when the Main power plane is shut down, although there may be small subsections powered. Note:The PCH power is not controlled by the SLP_S3# signal, but instead by the SLP_PRIM#signal.
Memory	SLP_S4# signal SLP_S5# signal	When SLP_S4# goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When SLP_S5# goes active, power can be shut off to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut down.
Intel^® CSME	SLP_A#	SLP_A# signal is asserted when the Intel^® CSME goes to M-Off or M3-PG. Depending on the platform, this pin may be used to control power to various devices that are part of the Intel^® CSME sub-system in the platform.
LAN	SLP_LAN#	This signal is asserted in Sx/M-Off or Sx/M3-PG when both host and Intel^® CSME WoL are not supported. This signal can be use to control power to the Platform LAN Connect Device.
Primary Well	SLP_PRIM#	This signal is asserted when the Primary rails can be externally shut off for enhanced power saving.
VCCIO and VCCSTG	CPU_C10_GATE#	This signal is asserted when the processor enters C10 and can handle VCCIO, VCCSTG and VCCPLL_OC being lowered to 0 V.
DEVICE[n]	GPIO	Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen.