PWRBTN# (Power Button)

The PWRBTN# signal operates as a “Fixed Power Button” as described in the Advanced Configuration and Power Interface Specification. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition descriptions are included in the below table.

After any PWRBTN# assertion (falling edge), the 16 ms de-bounce applies before the state transition starts if PB_​DB_​MODE=’0’. If PB_​DB_​MODE=’1’, the state transition starts right after any PWRBTN# assertion (before passing through the debounce logic) and subsequent falling PWRBTN# edges are ignored until after 16 ms.

During the time that any SLP_​* signal is stretched for an enabled minimum assertion width, the host wake-up is held off. As a result, it is possible that the user will press and continue to hold the Power Button waiting for the system to wake. Unfortunately, a 4 second press of the Power Button is defined as an unconditional power down, resulting in the opposite behavior that the user was intending. Therefore, the Power Button Override Timer will be extended to 9-10 seconds while the SLP_​* stretching timers are in progress. Once the stretching timers have expired, the Power Button will awake the system. If the user continues to press Power Button for the remainder of the 9-10 seconds it will result in the override condition to S5. Extension of the Power Button Override timer is only enforced following graceful sleep entry and during host partition resets with power cycle or power down. The timer is not extended immediately following power restoration after a global reset and G3/Deep Sx.

The PCH also supports modifying the length of time the Power Button must remain asserted before the unconditional power down occurs (4-14 seconds). The length of the Power Button override duration has no impact on the “extension” of the power button override timer while SLP_​* stretching is in progress. The extended power button override period while stretching is in progress remains 9-10 seconds in all cases.

Power Button Override Function

If PWRBTN# is observed active for at least four consecutive seconds (always sampled after the output from debounce logic), the PCH should unconditionally transition to the G2/S5 state or Deep Sx, regardless of present state (S0 – S4), even if the PCH_​PWROK is not active. In this case, the transition to the G2/S5 state or Deep Sx does not depend on any particular response from the processor, nor any similar dependency from any other subsystem.

The minimum period is configurable by BIOS and defaults to the legacy value of 4 seconds.

The PWRBTN# status is readable to check if the button is currently being pressed or has been released. If PM_​CFG.PB_​DB_​MODE=’0’, the status is taken after the de-bounce. If PM_​CFG.PB_​DB_​MODE=’1’, the status is taken before the de-bounce. In either case, the status is readable using the PWRBTN_​LVL bit.

Sleep Button

The Advanced Configuration and Power Interface Specification defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the Sleep Button cannot.

Although the PCH does not include a specific signal designated as a Sleep Button, one of the GPIO signals can be used to create a “Control Method” Sleep Button. Refer to Advanced Configuration and Power Interface Specification for implementation details.

PME# (PCI Power Management Event)

The PME# signal comes from a PCI Express* device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a wake event. The event occurs when the PME# signal goes from high to low. No event is caused when it goes from low to high.

There is also an internal PME_​B0_​STS bit (replaced PME_​B0 bit) that will be set by the PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. This is separate from the external PME# signal and can cause the same effect.

SYS_​RESET# Signal

When the SYS_​RESET# pin is detected as active (on signal’s falling edge if de-bounce logic is disabled, or after 16 ms if 16 ms debounce logic is enabled), the PCH attempts to perform a “graceful” reset by entering a host partition reset entry sequence.

Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYS_​RESET# input remains asserted or not. It cannot occur again until SYS_​RESET# has been detected inactive after the de-bounce logic, and the system is back to a full S0 state with PLTRST# inactive.

Sx_​Exit_​Holdoff#

When S4/S5 is entered and SLP_​A# is asserted, Sx_​Exit_​Holdoff# can be asserted by a platform component to delay resume to S0. SLP_​A# de-assertion is an indication of the intent to resume to S0, but this will be delayed so long as Sx_​Exit_​Holdoff# is asserted. Sx_​Exit_​Holdoff is ignored outside of an S4/S5 entry sequence with SLP_​A# asserted. With the de-assertion of PCH_​RSMRST# (either from G3->S0 or DeepSx->S0), this pin is a GPIO input and must be programmed by BIOS to operate as Sx_​Exit_​Holdoff. When SLP_​A# is asserted (or it is de-asserted but Sx_​Exit_​Holdoff# is asserted), the PCH will not access SPI Flash. How a platform uses this signal is platform specific.

Requirements to Support Sx_​Exit_​Holdoff#

If the PCH is in G3/DeepSx or in the process of exiting G3/DeepSx (PCH_​RSMRST# is asserted), the EC must not allow PCH_​RSMRST# to de-assert until the EC completed its flash accesses.

After the PCH has booted up to S0 at least once since the last G3 or DeepSx exit, the EC can begin monitoring SLP_​A# and using the SX_​EXIT_​HOLDOFF# pin to stop the PCH from accessing flash. When SLP_​A# asserts, if the EC intends to access flash, it will assert SX_​EXIT_​HOLDOFF#. To cover the case where the PCH is going through a global reset, and not a graceful Sx+CMoff/Sx+CM3PG entry, the EC must monitor the SPI flash CS0# pin for 5 ms after SLP_​A# assertion before making the determination that it is safe to access flash.

• If no flash activity is seen within this 5 ms window, the EC can begin accessing flash. Once its flash accesses are complete, the EC de-asserts (drives to ‘1’) SX_​EXIT_​HOLDOFF# to allow the PCH to access flash.
• If flash activity is seen within this 5 ms window, the PCH has gone through a global reset. And so the EC must wait until the PCH reaches S0 again before re-attempting the holdoff flow.

Note:When eSPI is enabled, SX_​EXIT_​HOLDOFF# functionality is not available, and assertion of the signal will not impact Sx exit flows.