Intel® 800 Series Chipset Family Platform Controller Hub (PCH)

Datasheet, Volume 1 of 2

ID Date Version Classification
833778 01/07/2025 Public
Document Table of Contents

I/O Signal Planes and States

Signal Name

Power Plane

During Reset1

Immediately after Reset1

S4/S5

DIR_​ESPI_​IO [3:0]

Primary

Internal Pull-up

Internal Pull-up

Internal Pull-up

DIR_​ESPI_​CLK

Primary

Internal Pull- down

Driven Low

Driven Low

DIR_​ESPI_​RCLK Primary Internal Pull- down Driven Low Driven Low

DIR_​ESPI_​ CS#

Primary

Internal Pull-up

Driven High

Driven High

DIR_​ESPI_​ALERT#

Primary

Internal Pull-up

Internal Pull-up

Internal Pull-up

DIR_​ESPI_​RESET#

Primary

Driven Low

Driven High

Driven High

Note:Reset reference for primary well pins is PCH_​RSMRST#.