Intel® 800 Series Chipset Family Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 833778 | 01/07/2025 | Public |
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Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
Audio Voice and Speech
Ballout Definition
Connectivity Integrated (CNVi)
Controller Link
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Direct Media Interface (DMI)
Enhanced Serial Peripheral Interface (eSPI)
Gigabit Ethernet Controller
Host System Management Bus (SMBus) Controller
Integrated Sensor Hub (ISH)
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers
PCI Express* (PCIe*)
Real Time Clock (RTC)
Serial ATA (SATA)
Serial Peripheral Interface (SPI)
System Clocks
System Management Interface and SMLink
Touch Host Controller (THC)
Universal Serial Bus (USB)
General Purpose Input and Output
GPIO Serial Expander
Private Configuration Space Port ID
Security Firmware Engines
System Management
Testability and Monitoring
Miscellaneous Signals
Processor Sideband Signals
Power Delivery
Power Management
Thermal Sensor
Electrical Characteristics
Audio Voice and Speech
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S / PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Configuration Flow
PCH Direct eSPI Registers
PCH Direct eSPI Reset Handling
PCH Direct eSPI Peripheral Channel Support
PCH Direct eSPI VW Channel Support
PCH Direct eSPI OOB Channel Support
PCH Direct eSPI Flash Channel Support
PCH eSPI Switch
Flash Descriptor Address Swapping
Interrupts
Each interface has the ability to interrupt and notify the driver that service is required
When an interrupt occurs, the device driver needs to read both the host controller and DMA interrupt status and transmit completion interrupt registers to identify the interrupt source. Clearing the interrupt is done with the corresponding interrupt register in the host controller or DMA.