PCH Direct eSPI Peripheral Channel Support

The PCH Direct eSPI target forwards the received peripheral channel IO/memory cycles from the processor Direct eSPI, PCH eSPI, or PCH internal from/to the upper layer eSPI switch. The eSPI switch then decodes the address and forwards it to the corresponding destination (Ex. EC, other IP) accordingly.

The PCH Direct eSPI target defers the downstream non-posted cycle and sends back the completion. The order of the Posted/Non-Posted cycles in both directions enforced to follow the eSPI ordering rule in the eSPI base spec "5.4 Transaction Ordering Rule".

The peripheral channel is enabled automatically after PLTRST# deassertion (tunneled as a VW). The peripheral channel is enabled before any downstream transactions are delivered. The PCH Direct eSPI target will not send upstream bus controlling requests until the Direct eSPI BME bit has been set..

In preparation for host reset, the processor Direct eSPI controller completes all downstream peripheral channel (P/Ch.) pending transactions and quiesces all its P/Ch request queues before sending the VW Host_​Reset_​Warn to the PCH Direct eSPI target. The PCH Direct eSPI target completes all P/Ch pending transactions (including downstream completions) and quiesces all upstream P/Ch request queues before sending Host_​Reset_​Ack VW back to the processor Direct eSPI controller. The PCH Direct eSPI target must continue to be able to receive downstream posted transactions until the channel is disabled with the assertion of PLTRST# (tunneled as VW). After sending the HOST_​RST_​ACK, the PCH Direct eSPI target does not send any peripheral channel transaction.

The PCH Direct eSPI controller automatically clears the P/Ch enable bit and BME bit upon PLTRST# assertion (tunneled as VW) set by BIOS.

A host reset Warn/Ack handshake (using VWs) will always accompany the assertion of PLTRST# (tunneled as a VW). The PCH Direct eSPI target Status register's P/Ch bits are cleared and locked after sending the Host_​Reset_​Ack VW. The host re-enables the P/Ch.

An unplanned reset event in the processor or the PCH might cause an abrupt assertion of PLTRST# and ESPI_​RESET#, abruptly terminating any pending requests/completions, without a reset Warn/Ack handshake. In this scenario, the PLTRST# assertion is not tunneled as VW. The Direct eSPI interface, all channels, and all VWs revert back to their default states due to the simultaneous assertion of ESPI_​RESET#.