Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers

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Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
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I³C specification is backward compatible with I²C devices. The I³C enables dynamic address allocation and inband interrupts. The Spec also allows for hot-plug / hot-join of devices. The I³C Specification is backward compatible with legacy I²C devices and enables coexistence of legacy I²C and I³C devices on the same bus in Fast Mode, Fast Mode Plus modes, without clock stretching. The PCH has one I³C controller compliant to MIPI I³C HCI Specification, that can support 2 I³C buses and up to 8 devices per bus (subject to meeting electrical/topology requirements).

The I³C interfaces support the following features:

Support for MIPI I³C spec v1.0, and MIPI I³C HCI Specification

Speed: standard mode (up to 100 Kb/s), fast mode (up to 400 Kb/s), fast mode plus (up to 1 MB/s)

Supports clock loopback using dummy IO to meet ACIO timing

Maximum theoretical Baud rate is 12900 kbps

Maximum validated Baud rate is 12500 kbps

Operate in 1.8 V Only

DMA support with 64-byte DMA FIFO per channel (up to 32-byte burst)

64-byte Tx FIFO and 64-byte Rx FIFO

PME/wake support for IBI, when in S0ix

PCI/ACPI enumeration support

I³C static addressing and dynamic addressing support

I³C in-band interrupt

I³C transactions using SDR

Error detection and recovery methods M0, M2

For stalling Host clock on data buffering

Host I³C operation only

Notes:

The controllers must only be programmed to operate in Host mode only. I³C Device mode is not supported.

I³C multi Hosts is not supported.

Simultaneous configuration of Fast Mode and Fast Mode Plus is not supported.

Acronyms

Acronyms	Description
I³C	Improved Inter-Integrated Circuit
SCL	Serial Clock Line
SDA	Serial Data Line

Reset

I/O Signal Planes and States Reset