| GPP_E04/SATA_DEVSLP0 | I or O | Serial ATA Port [0] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 0. |
| GPP_E05/SATA_DEVSLP1 | I or O | Serial ATA Port [1] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 1. |
| GPP_E06/SATA_DEVSLP2 | I or O | Serial ATA Port [2] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 2. |
| GPP_F05/SATA_DEVSLP3 | I or O | Serial ATA Port [3] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 3. |
| GPP_F06/SATA_DEVSLP4 | I or O | Serial ATA Port [4] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 4. |
| GPP_F07/SATA_DEVSLP5 | I or O | Serial ATA Port [5] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 5. |
| GPP_F08/SATA_DEVSLP6 | I or O | Serial ATA Port [6] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 6. |
| GPP_F09/SATA_DEVSLP7 | I or O | Serial ATA Port [7] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. Design Constraint: no external Pull-up or Pull-down termination required when used as DEVSLP. This pin can be mapped to SATA Port 7. |
| PCIE_13_TXN/SATA_0_TXN PCIE_13_TXP/SATA_0_TXP | O | Serial ATA Differential Transmit Pair 0: These outbound SATA Port 0 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_13_RXN/SATA_0_RXN PCIE_13_RXP/SATA_0_RXP | I | Serial ATA Differential Receive Pair 0: These inbound SATA Port 0 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_14_TXN/SATA_1_TXN PCIE_14_TXP/SATA_1_TXP | O | Serial ATA Differential Transmit Pair 1 :These outbound SATA Port 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_14_RXN/SATA_1_RXN PCIE_14_RXP/SATA_1_RXP | I | Serial ATA Differential Receive Pair 1: These inbound SATA Port 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_15_TXP/SATA_2_TXP/GbE_0C_TXP PCIE_15_TXN/SATA_2_TXN/GbE_0C_TXN | O | Serial ATA Differential Transmit Pair 2: These outbound SATA Port 2 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_15_RXP/SATA_2_RXP/GbE_0C_RXP PCIE_15_RXN/SATA_2_RXN/GbE_0C_RXN | I | Serial ATA Differential Receive Pair 2: These inbound SATA Port 2 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_16_TXP/SATA_3_TXP PCIE_16_TXN/SATA_3_TXN | O | Serial ATA Differential Transmit Pair 3: These outbound SATA Port 3 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_16_RXP/SATA_3_RXP PCIE_16_RXN/SATA_3_RXN | I | Serial ATA Differential Receive Pair 3: These inbound SATA Port 3 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_17_TXP/SATA_4_TXP PCIE_17_TXN/SATA_4_TXN | O | Serial ATA Differential Transmit Pair 4: These outbound SATA Port 4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_17_RXP/SATA_4_RXP PCIE_17_RXN/SATA_4_RXN | I | Serial ATA Differential Receive Pair 4: These inbound SATA Port 4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_18_TXP/SATA_5_TXP PCIE_18_TXN/SATA_5_TXN | O | Serial ATA Differential Transmit Pair 5: These outbound SATA Port 5 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_18_RXP/SATA_5_RXP PCIE_18_RXN/SATA_5_RXN | I | Serial ATA Differential Receive Pair 5: These inbound SATA Port 5 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_19_TXP/SATA_6_TXP PCIE_19_TXN/SATA_6_TXN | O | Serial ATA Differential Transmit Pair 6: These outbound SATA Port 6 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_19_RXP/SATA_6_RXP PCIE_19_RXN/SATA_6_RXN | I | Serial ATA Differential Receive Pair 6: These inbound SATA Port 6 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_20_TXP/SATA_7_TXP PCIE_20_TXN/SATA_7_TXN | O | Serial ATA Differential Transmit Pair 7: These outbound SATA Port 7 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE_20_RXP/SATA_7_RXP PCIE_20_RXN/SATA_7_RXN | I | Serial ATA Differential Receive Pair 7: These inbound SATA Port 7 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| GPP_E00/SATAXPCIE0/SATAGP0 | I | Serial ATA Port [0] General Purpose Inputs: When configured as SATAGP0, this is an input pin that is used as an interlock switch status indicator for SATA Port 0. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. The default use of this pin is GPP_E0.Pin defaults to Native mode as SATAXPCIE0(SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_E01/SATAXPCIE1/SATAGP1 | I | Serial ATA Port [1] General Purpose Inputs: When configured as SATAGP1, this is an input pin that is used as an interlock switch status indicator for SATA Port 1. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_E1.Pin defaults to Native mode as SATAXPCIE1 (SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_E02/SATAXPCIE2/SATAGP2 | I | Serial ATA Port [2] General Purpose Inputs: When configured as SATAGP2, this is an input pin that is used as an interlock switch status indicator for SATA Port 2. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_E2.Pin defaults to Native mode as SATAXPCIE2 (SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_F00/SATAXPCIE3/SATAGP3 | I | Serial ATA Port [3] General Purpose Inputs: When configured as SATAGP3, this is an input pin that is used as an interlock switch status indicator for SATA Port 3. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_F0.Pin defaults to Native mode as SATAXPCIE3 (SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_F01/SATAXPCIE4/SATAGP4 | I | Serial ATA Port [4] General Purpose Inputs: When configured as SATAGP4, this is an input pin that is used as an interlock switch status indicator for SATA Port 4. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_F1.Pin defaults to Native mode as SATAXPCIE4 (SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_F02/SATAXPCIE5/SATAGP5 | I | Serial ATA Port [5] General Purpose Inputs: When configured as SATAGP5, this is an input pin that is used as an interlock switch status indicator for SATA Port 1. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_F2.Pin defaults to Native mode as SATAXPCIE5 (SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_F03/SATAXPCIE6/SATAGP6 | I | Serial ATA Port [6] General Purpose Inputs: When configured as SATAGP6, this is an input pin that is used as an interlock switch status indicator for SATA Port 6. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_F3.Pin defaults to Native mode as SATAXPCIE6 (SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_F04/SATAXPCIE7/SATAGP7 | I | Serial ATA Port [7] General Purpose Inputs: When configured as SATAGP7, this is an input pin that is used as an interlock switch status indicator for SATA Port 1. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_F4.Pin defaults to Native mode as SATAXPCIE7 (SATA [bit0] or PCIe* [bit1] combo lanes selection) depends on soft-strap. |
| GPP_E08/SATALED# | I or O | Serial ATA LED: This signal is an open-drain output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external Pull-up resistor to VCC1P8 is required. |
| GPP_F13/SATA_SDATAOUT0 | O | Serial ATA GPIO Data Output 0 :Enclosure Management SGPIO Dataout 0 to indicate the drive status |
| GPP_F12/SATA_SDATAOUT1 | O | Serial ATA GPIO Data Output 1 :Enclosure Management SGPIO Dataout 1 to indicate the drive status |
| GPP_F11/SATA_SLOAD | I or O | Serial ATA GPIO Load Signal :Enclosure Management SGPIO Load to indicate either the start or end of a bit stream. |
| GPP_F10/SATA_SCLOCK | I or O | Serial ATA GPIO Reference Clock :Enclosure Management SGPIO Reference Clock |