Intel® 800 Series Chipset Family Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
Memory Map
The following table shows (from the processor perspective) the memory ranges that the PCH will decode.
PCIe cycles generated by external PCIe hosts will be positively decoded unless they fall in the PCI-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer traffic). Software must not attempt locks to the PCH memory-mapped I/O ranges.
| Memory Range | Target | Dependency/Comments |
|---|---|---|
| 000E 0000 - 000E FFFF | eSPI or SPI | Bit 6 in BIOS Decode Enable Register is set |
| 000F 0000 - 000F FFFF | eSPI or SPI | Bit 7 in BIOS Decode Enable Register is set |
| FEF0 0000 - FEFF FFFF | eSPI or SPI | uCode Patch Region Enable UCPR.UPRE is set |
| FFC0 0000 - FFC7 FFFF FF80 0000 - FF87 FFFF | eSPI or SPI | Bit 8 in BIOS Decode Enable Register is set |
| FFC8 0000 – FFCF FFFF FF88 0000 - FF8F FFFF | eSPI or SPI | Bit 9 in BIOS Decode Enable Register is set |
| FFD0 0000 - FFD7 FFFF FF90 0000 - FF97 FFFF | eSPI or SPI | Bit 10 in BIOS Decode Enable Register is set |
| FFD8 0000 – FFDF FFFF FF98 0000 - FF9F FFFF | eSPI or SPI | Bit 11 in BIOS Decode Enable Register is set |
| FFE0 0000 - FFE7 FFFF FFA0 0000 - FFA7 FFFF | eSPI or SPI | Bit 12 in BIOS Decode Enable Register is set |
| FFE8 0000 – FFEF FFFF FFA8 0000 – FFAF FFFF | eSPI or SPI | Bit 13 in BIOS Decode Enable Register is set |
| FFF0 0000 - FFF7 FFFF FFB0 0000 - FFB7 FFFF | eSPI or SPI | Bit 14 in BIOS Decode Enable Register is set |
| FFFC 0000 - FFFF FFFF | eSPI, SPI | Always enabled. |
| FFF8 0000 - FFFB FFFF FFB8 0000 - FFBF FFFF | eSPI or SPI | Always enabled. |
| FF70 0000 - FF7F FFFF FF30 0000 - FF3F FFFF | eSPI or SPI | Bit 3 in BIOS Decode Enable Register is set |
| FF60 0000 - FF6F FFFF FF20 0000 - FF2F FFFF | eSPI or SPI | Bit 2 in BIOS Decode Enable Register is set |
| FF50 0000 - FF5F FFFF FF10 0000 - FF1F FFFF | eSPI or SPI | Bit 1 in BIOS Decode Enable Register is set |
| FF40 0000 - FF4F FFFF FF00 0000 - FF0F FFFF | eSPI or SPI | Bit 0 in BIOS Decode Enable Register is set |
| FED4 0000 - FED4 7FFF | SPI (set by strap) | TPM and Trusted Mobile KBC |
| 128 KB anywhere in 4 GB range | LAN Controller (CSR registers) | Enable via standard PCI mechanism (Device 31:Function 6) |
| 4 KB anywhere in 4 GB range | LAN Controller (LAN space on Flash) | Enable via standard PCI mechanism (Device 31:Function 6) |
| 64 KB anywhere in 64-bit address range | USB 3.2 Host Controller | Enable via standard PCI mechanism (Device 20, Function 0) |
| 2 MB anywhere in 4 GB range | USB Device Controller | Enable via standard PCI mechanism (Device 20, Function 1) |
| 24 KB anywhere in 4 GB range | USB Device Controller | Enable via standard PCI mechanism (Device 20, Function 1) |
| 16 KB anywhere in 64-bit addressing space | Intel® HD Audio Subsystem | Enable via standard PCI mechanism (Device 31, Function 3) |
| 4 KB anywhere in 64-bit addressing space | Intel® HD Audio Subsystem | Enable via standard PCI mechanism (Device 31, Function 3) |
| 64 KB anywhere in 64-bit addressing space | Intel® HD Audio Subsystem | Enable via standard PCI mechanism (Device 31, Function 3) |
| 1MB anywhere in 4 GB range | eSPI | LPC Generic Memory Range. Enable via setting bit<wbr>[0] of the LPC Generic Memory Range register (D31:F0:offset 98h). |
| 64 KB anywhere in 4 GB range | eSPI | eSPI Generic Memory Range (for the 2nd, 3rd and 4th eSPI CS#). Enable bit via setting bit<wbr>[0] of the respective Memory Range register (D31:F0) |
| 32 Bytes anywhere in 64-bit address range | SMBus | Enable via standard PCI mechanism (Device 31: Function 4) |
| 2 KB anywhere above 64 KB to 4 GB range | SATA Host Controller | AHCI memory-mapped registers. Enable via standard PCI mechanism (Device 23: Function 0) |
| Memory Base/Limit anywhere in 4 GB range | PCI Express* Root Ports 1-24 | Enable via standard PCI mechanism |
| Prefetchable Memory Base/Limit anywhere in 64-bit address range | PCI Express* Root Ports 1-24 | Enable via standard PCI mechanism |
| 16 Bytes anywhere in 64-bit address range | Intel® CSMEI #1, #2, #3, #4 | Enable via standard PCI mechanism |
| 4 KB anywhere in 4 GB range | Intel® AMT Keyboard and Text | Enable via standard PCI mechanism (Device 22: Function 3) |
| 16 MB anywhere in 64-bit address range | P2SB | Enable via standard PCI mechanism |
| 12 4 KB slots anywhere in 64-bit address range | I3C function has 8 KB BAR, all others (I2C/SPI/UART) are 4 KB. | Enable via standard PCI mechanism |
| 1 MB (BAR0) or 4 KB (BAR1) in 4GB range | Integrated Sensor Hub | Enable via standard PCI mechanism (Device 19: Function 0) |
| 8 KB slot anywhere in 4 GB range | Integrated Wi-Fi* | Enable via standard PCI mechanism |
| 8 KB slot and 4 KB slot anywhere in 4 GB range | PMC | Enable via standard PCI mechanism |
| 8 KB slot and 4 KB slot anywhere in 4 GB range | Shared SRAM | Enable via standard PCI mechanism |
| Two 32 KB anywhere in 64-bit address range | THC #0, #1 | Enable via standard PCI mechanism |
| DMI General Purpose Memory ranges (1 to 3) | General purpose | Enable via setting the Decode Enable bit of the respective Memory Range register |
| MMIO resources for VMD managed devices | Storage devices | Enable through the VMD device in PCH |