GPD01/ACPRESENT

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ACPRESENT: This input pin indicates when the platform is plugged into AC power or not. In addition to Intel^® CSME to EC communication, the PCH uses this information to implement the Deep Sx policies. For example, the platform may be configured to enter Deep Sx when in S4 or S5 and only when running on battery.

GPD00/BATLOW#

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Battery Low: An input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S4/S5 states or exit from Deep Sx state. This signal can also be enabled to cause an SMI# when asserted. This signal is multiplexed with GPD0.

DSW_​PWROK

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DeepSx Well PWROK: Power OK Indication for the VCCDSW_​3p3 voltage rail. Note:This signal is in the RTC well.

For non-Deep Sx implementation DSW_​PWROK is tied to PCH_​RSMRST#. DSW_​PWROK goes high with PCH_​RSMRST# after PRIM rail complete ramp

For Deep Sx Implementation DSW_​PWROK and PCH_​RSMRST# are separate signals and should not be tied

GPD02/LAN_​WAKE#

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LAN WAKE: An active low wake indicator from the Platform LAN Connect Device.

GPD11/LANPHYPC

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LAN PHY Power Control: LANPHYPC is used to indicate that power needs to be restored to the Platform LAN Connect Device.

PCH_​PWROK

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PCH Power OK: When asserted, is an indication to the PCH that all of its core power rails have been stable. The platform may drive asynchronously. When is de-asserted, the PCH asserts PLTRST#.

GPP_​B13/PLTRST#

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Platform Reset: The PCH asserts PLTRST# to reset devices on the platform. The PCH asserts PLTRST# low in Sx states and when a cold, warm, or global reset occurs. The PCH de-asserts PLTRST# upon exit from Sx states and the aforementioned resets. There is no guaranteed minimum assertion time for PLTRST#.

GPP_​B18/PMCALERT#

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PMC Alert Pin: Supports USB-C* PD controller architecture.

GPD03/PWRBTN#

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Power Button: The Power Button may cause an SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds (default; timing is configurable), this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S4 states. This signal has an internal Pull-up resistor and has an internal 16 ms de-bounce on the input.

PCH_​RSMRST#

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Primary Well Reset: This signal is used for resetting the primary power plane logic. This signal must be asserted for at least 10ms before de-asserting.

GPD06/SLP_​A#

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SLP_​A#: Signal asserted when the Intel^® CSME platform goes to M-Off or M3-PG. Depending on the platform, this pin may be used to control power to various devices that are part of the Intel^® CSME sub-system in the platform. If you are not using SLP_​A# for any functional purposes on your platform, or can tolerate lack of minimum assertion time, program the "SLP_​A# minimum assertion width" value to the minimum.

SLP_​A# functionality can be utilized on the platform via either the physical pin or via the SLP_​A# virtual wire over eSPI.

SLP_​LAN#

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LAN Sub-System Sleep Control: When SLP_​LAN# is de-asserted it indicates that the Platform LAN Connect Device must be powered. When SLP_​LAN# is asserted, power can be shut off to the Platform LAN Connect Device. SLP_​LAN# will always be de-asserted in S0 and anytime SLP_​A# is de-asserted.

GPD09/SLP_​WLAN#

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WLAN Sub-System Sleep Control: When SLP_​WLAN# is asserted, power can be shut off to the external wireless LAN device. SLP_​WLAN# will always will be de-asserted in S0. If you are not using SLP_​WLAN# for any functional purposes on your platform, or can tolerate lack of minimum assertion time, program the "SLP_​A# minimum assertion width" value to the minimum.

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GPD05/SLP_​S4#

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S4 Sleep Control: SLP_​S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 or S5 state.

GPD10/SLP_​S5#

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S5 Sleep Control: SLP_​S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 state.

SLP_​PRIM#

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Deep Sx Indication: When asserted (driven low), this signal indicates PCH is in Deep Sx state where internal primary power is shut off for enhanced power saving. When de-asserted (driven high), this signal indicates exit from Deep Sx state and primary power can be applied to PCH. If Deep Sx is not supported, then this pin need to connect to VCCPRIM_​1P8.

GPP_​A03/ESPI_​IO3/PRIMACK#

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PRIMACK#: If Deep Sx is supported, the EC/motherboard controlling logic must change PRIMACK# to match PRIMWARN# once the EC/motherboard controlling logic has completed the preparations discussed in the description for the PRIMWARN# pin.

GPD08/SUSCLK

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Suspend Clock: This clock is a digitally buffered version of the RTC clock.

GPP_​A02/ESPI_​IO2/PRIMWARN#/PRIMPWRDNACK

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PRIMWARN#: This pin asserts low when the PCH is planning to enter the Deep Sx power state and remove Primary power (using SLP_​PRIM#). The EC/motherboard controlling logic must observe edges on this pin, preparing for primary well power loss on a falling edge and preparing for Primary well related activity (host/Intel CSME wakes and runtime events) on a rising edge. PRIMACK# must be driven to match PRIMWARN# once the above preparation is complete. PRIMACK# should be asserted within a minimal amount of time from PRIMWARN# assertion as no wake events are supported if PRIMWARN# is asserted but PRIMACK# is not asserted. Platforms supporting Deep Sx, but not wishing to participate in the handshake during wake and Deep Sx entry may tie PRIMACK# to PRIMWARN#.

This pin is multiplexed with PRIMPWRDNACK since it is not needed in Deep Sx supported platforms.

GPP_​A02/ESPI_​IO2/PRIMWARN#/PRIMPWRDNACK

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PRIMPWRDNACK: Active high. Asserted by the PCH on behalf of the Intel CSME when it does not require the PCH Primary well to be powered.

Platforms are not expected to use this signal when the PCH Deep Sx feature is used.

GPP_​B05/SX_​EXIT_​HOLDOFF#/ISH_​GP6

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Sx Exit Holdoff Delay: Delay exit from Sx state after SLP_​A# is de-asserted. Note:When eSPI is enabled, the flash sharing functionality using SX_​EXIT_​HOLDOFF# is not supported, but the pin still functions to hold off Sx exit after SLP_​A# de-assertion.

SYS_​RESET#

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System Reset: This pin forces an internal reset after being de-bounced.

WAKE#

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PCI Express* Wake Event in Sx: Input Pin in Sx. Sideband wake signal on PCI Express* asserted by components requesting wake up.

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An early indication that the Processor has detected a condition that will cause it to signal the system to perform a power cycle

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Bidirectional signal used to synchronize reset events between the processor and PCH.

Sync reset exits with the PCH in following two steps:

1. The processor floats the RESET_​SYNC# pin to allow it to be pulled high by the platform.
2. The processor waits until it sees the RESET_​SYNC# pin go high before proceeding to reset exit.

The PCH will stop driving the pin low when the eSPI controller in the PCH is out of reset and ready to receive traffic over the eSPI link. It is required that the PCH eSPI controller is ready before the Processor eSPI controller is released from reset.