Intel® 800 Series Chipset Family Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 833778 | 01/07/2025 | Public |
Flash Descriptor Address Swapping
The processor and the PCH share the same flash on PCH side either in SAF or MAF mode. Both components require its own version of the descriptors.
The processor transparently accesses the descriptor. The PCH eSPI controller swaps the flash read/write cycles from the processor with an address within 0-12KB to 12-24KB on PCH flash (MAF or SAF).
From the PCH SPI controller perspective, the PCH descriptor (including main and two backups) is in region 0, located at the flash address 0-12KB, while the processor descriptor (including main and two backups) is in the region located at flash address 12KB-24KB.
From the processor SPI controller perspective, due to the swapping, the processor descriptor (including main and two backups) is in region 0, located at the flash address 0-12KB, while the PCH descriptor (including the main and two backups) is in the region located at flash address 12KB-24KB.
The descriptor regions shown in the diagram below. The two versions of the descriptors use two separate regions to allow independent access permissions control on the processor and the PCH descriptors.