Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers

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The implements six I²C controllers for six independent I²C interfaces, I2C0-I2C5. Each interface is a two-wire serial interface consisting of a serial data line (SDA) and a serial clock (SCL).

The I²C interfaces support the following features:

Speed: standard mode (up to 100 Kb/s), fast mode (up to 400 Kb/s), fast mode plus (up to 1 MB/s) and High speed mode (up to 3.2 Mb/s).

Operate in 1.8 V or 3.3 V

Host I²C operation only

7-bit or 10-bit addressing

7-bit or 10-bit combined format transfers

Bulk transmit mode

Ignoring CBUS addresses (an older ancestor of I²C used to share the I²C bus)

Interrupt or polled-mode operation

Bit and byte waiting at all bus speed

Component parameters for configurable software driver support

Programmable SDA hold time (tHD; DAT)

DMA support with 64-byte DMA FIFO per channel (up to 32-byte burst)

64-byte Tx FIFO and 64-byte Rx FIFO

SW controlled serial data line (SDA) and serial clock (SCL)

Notes:

The controllers must only be programmed to operate in Host mode only. I²C device mode is not supported.

I²C multi hosts is not supported.

Simultaneous configuration of Fast Mode and Fast Mode Plus/High speed mode is not supported.

I²C General Call is not supported.

Acronyms

Acronyms	Description
I²C	Inter-Integrated Circuit
PIO	Programmed Input/Output
SCL	Serial Clock Line
SDA	Serial Data Line

References

Specification	Location
The I²C Bus Specification, Version 5	www.nxp.com/documents/user_manual/UM10204.pdf

Functional Description

I/O Signal Planes and States Functional Description