Revision IDs

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Revision History
Introduction
PCH Controller Device IDs
- Revision IDs
- Device IDs
Memory Mapping
- Functional Description
- Memory Map
Audio Voice and Speech
Ballout Definition
Connectivity Integrated (CNVi)
Controller Link
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Direct Media Interface (DMI)
Enhanced Serial Peripheral Interface (eSPI)
Gigabit Ethernet Controller
Host System Management Bus (SMBus) Controller
Integrated Sensor Hub (ISH)
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers
PCI Express* (PCIe*)
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Serial ATA (SATA)
Serial Peripheral Interface (SPI)
System Clocks
- Integrated Clock Controller (ICC)
  - Signal Descriptions
- I/O Signal Pin States
System Management Interface and SMLink
Touch Host Controller (THC)
Universal Serial Bus (USB)
General Purpose Input and Output
- Functional Description
- Signal Description
GPIO Serial Expander
Private Configuration Space Port ID
Security Firmware Engines
- Intel® Converged Security and Management Engine (Intel® CSME)
- Intel® Silicon Security Engine
System Management
- Theory of Operation
  - TCO Modes
Testability and Monitoring
- Signal Description
- I/O Signal Planes and States
Miscellaneous Signals
Processor Sideband Signals
- Signal Description
- I/O Signal Planes and States
Power Delivery
- Power and Ground Signals
Power Management
Thermal Sensor
Electrical Characteristics

The Revision ID (RID) register is an 8-bit register located at offset 08h in the PCI header of every PCI/PCIe* function.

Device IDs

PCH Controller Device IDs Device IDs