Intel® 800 Series Chipset Family Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 833778 | 02/06/2025 | Public |
PCH Direct eSPI Flash Channel Support
The PCH Direct eSPI device target supports SAF mode, including RPMC. For RPMC support, the PCH Direct eSPI parameters in the SAF capability and configuration registers are sourced from either SPI Flash's RPMC SFDP table or EC's SAF RPMC register depending on the PCH's flash sharing mode.
The PCH eSPI controller reads the "Device 0" SAF registers (0x40 and 0x44) and saves them inside the controller in the private registers. The PCH SPI controller reads the SFDP RPMC register and saves it inside the controller in the private registers.
The PCH Direct eSPI target uses either of these two sets of parameters depending on the MAF or SAF mode and initializes the device's SAF 0x40/0x44 register.
Only one RPMC flash device is supported on device 0 in SAF mode. In SAF mode, the PCH Direct eSPI target defers the SAF cycles from the connected processor Direct eSPI controller. It forwards the SAF requests to the PCH eSPI host controller. When it receives the completion back from the PCH eSPI host controller, the PCH Direct eSPI target asserts an interrupt/flash_c_avail to send the completion back to the processor.