| CLKOUT_PCIE_N0 CLKOUT_PCIE_N1 CLKOUT_PCIE_N2 CLKOUT_PCIE_N3 CLKOUT_PCIE_N4 CLKOUT_PCIE_N5 CLKOUT_PCIE_N6 CLKOUT_PCIE_N7 CLKOUT_PCIE_N8 CLKOUT_PCIE_N9 CLKOUT_PCIE_N10 CLKOUT_PCIE_N11 CLKOUT_PCIE_N12 CLKOUT_PCIE_N13 CLKOUT_PCIE_P0 CLKOUT_PCIE_P1 CLKOUT_PCIE_P2 CLKOUT_PCIE_P3 CLKOUT_PCIE_P4 CLKOUT_PCIE_P5 CLKOUT_PCIE_P6 CLKOUT_PCIE_P7 CLKOUT_PCIE_P8 CLKOUT_PCIE_P9 CLKOUT_PCIE_P10 CLKOUT_PCIE_P11 CLKOUT_PCIE_P12 CLKOUT_PCIE_P13 | O | Yes | PCI Express* Clock Output: Serial Reference 100 MHz PCIe* specification compliant differential output clocks to PCIe* devices. CLKOUT_PCIE_P/N [13:0] is used for PCIe* Gen4 support. |
| GPP_D00/SRCCLKREQ0# GPP_D01/SRCCLKREQ1# GPP_D02/SRCCLKREQ2# GPP_D03/SRCCLKREQ3# GPP_D11/SRCCLKREQ4# GPP_D12/SRCCLKREQ5# GPP_D13/SRCCLKREQ6# GPP_D14/SRCCLKREQ7# GPP_H01/SRCCLKREQ8#/USB-C_GPP_H01 GPP_H02/SRCCLKREQ9#/USB-C_GPP_H02 GPP_H03/SRCCLKREQ10#/USB-C_GPP_H03 GPP_H04/SRCCLKREQ11#/USB-C_GPP_H04 GPP_E09/SRCCLKREQ12# GPP_E10/SRCCLKREQ13# | IOD | | Clock Request: Serial Reference Clock request signals for PCIe* 100 MHz differential clocks. |
| XTAL_IN | I | | Crystal Input: Input connection for 38.4 MHz crystal to PCH. |
| XTAL_OUT | O | | Crystal Output: Output connection for 38.4 MHz crystal to PCH. |
| CLKOUT_XTAL_P CLKOUT_XTAL_N | O | | 38.4 MHz XTAL NS clock output to Processor. |
| GPP_J08/RTCCLKOUT | O | | A form of RTC clock from the PCH to the processor which is active in S0, S0ix, and Sx. |
| EXT_INJ_P EXT_INJ_N | I | | External injected differential clock input for DMI overclocking. |
| DMI_CLKREQ# | IOD | | Clock Request: Clock request for DMI controller. |
| PCIE_EXTREFCLKN PCIE_EXTREFCLKP | I | | External Differential Reference Clock Input - for PCIe. |
- SSC = Spread Spectrum Clocking. Intel does not recommend changing the Plan of Record and fully validated SSC default value set in BIOS Reference Code. The SSC level must only be adjusted for debugging or testing efforts and any Non POR configuration setting used are the sole responsibility of the customer.
- The SRCCLKREQ# signals can be configured to map to any of the PCI Express* Root Ports while using any of the CLKOUT differential pairs.
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