12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
655258 05/25/2022 Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

Ground and Reserved Signals

The following are the general types of reserved (RSVD) signals and connection guidelines:

  • RSVD – these signals should not be connected
  • RSVD_​TP – these signals should be routed to a test point
  • _​NCTF – these signals are non-critical to function and should not be connected.

Arbitrary connection of these signals to VCC, VDD2, VSS, or to any other signal (including each other) may result in component malfunction or incompatibility with future processors. Refer to the table below.

For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs may be left unconnected however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing and prevent boundary scan testing. A resistor should be used when tying bi-directional signals to power or ground. When tying any signal to power or ground the resistor can also be used for system testability. Resistor values should be within ±20% of the impedance of the baseboard trace, unless otherwise noted in the appropriate platform design guidelines.

GND, RSVD, and NCTF Signals

Signal Name

Description

VSS

Ground: Processor ground node

VSS_​NCTF

Non-Critical To Function: These signals are for package mechanical reliability and should not be connected on the board.

RSVD

Reserved: All signals that are RSVD should not be connected on the board.

RSVD_​NCTF

Reserved Non-Critical To Function: RSVD_​NCTF should not be connected on the board.

RSVD_​TP

Test Point: Intel recommends to route each RSVD_​TP to an accessible test point. Intel may require these test points for platform specific debug. Leaving these test points inaccessible could delay debug by Intel.