| EKEY | Socket Electronic Key Used to distinguish between packages with different pins assignment. Connect this pin to the Enable signal of the first VR in sequence. Or as appropriate, to shut down complete power to SOC/platform when a wrong package is being used. | NA | NA | SE | S-Processor Line |
| SKTOCC# | Socket Occupied: Pulled down directly (0 Ohms) on the processor package to the ground. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present. | NA | NA | SE | S-Processor Line H-Processor Line P-Processor Line U-Processor Line |
| CFG[17:0] | Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. Intel recommends placing test points on the board for CFG pins. - CFG[2]: U9-Processor Line Reserved
- CFG[3]: Reserved configuration lane.
- CFG[4]: Reserved
- CFG[5] S-Processor Line PCI Express* Bifurcation
- 0 = 2 x8 PCI Express*
- 1 = 1 x16 PCI Express* (default)
- CFG[5] H/P/U15-Processor Line Reserved configuration lanes.
- CFG[6]: Reserved configuration lanes.
- CFG[7]: Reserved configuration lanes.
- CFG[13:8]: Reserved configuration lanes.
- CFG[14]: S-Processor Line PEG60 Lane Reversal:
- 1 - (Default) Normal
- 0 - Reversed
- CFG[14]: H/P/U15-Processor Line PEG60 Lane Reversal:
- 1 - (Default) Normal
- 0 - Reversed
- CFG[15]: H/P/U15-Processor Line PEG62 Lane Reversal:
- 1 - (Default) Normal
- 0 - Reversed
- CFG[14]: U9 Processor Line PEG60 Lane Reversal:
- 1 - (Default) Normal
- 0 - Reversed
- CFG[17:15]: U9 and S-Processor Line Reserved configuration lanes.
- CFG[17:16]: H/P/U15-Processor Line Reserved configuration lanes.
| I/O | GTL | SE | S-Processor Line H-Processor Line P-Processor Line U-Processor Line |
| CFG_RCOMP | Configuration Resistance Compensation | NA | NA | SE | H-Processor Line P-Processor Line U-Processor Line |
| VCC_CFG_PU_OUT | Power rail used by platform CFG straps for pull up resistors. | O | GTL | SE | S-Processor Line H-Processor Line P-Processor Line |
| EAR# | Stall reset sequence for early reset phases debug until deasserted: — 1 = (Default) Normal Operation; No stall. — 0 = Stall. | I | CMOS | SE | S-Processor Line H-Processor Line P-Processor Line U-Processor Line |
| RESET# | Platform Reset pin driven by the PCH. | I | CMOS | SE | S-Processor Line |
| CPU_ID | A PLATFORM indication signal, for Compatibility option. | | CMOS | SE | S-Processor Line H-Processor Line P-Processor Line U-Processor Line |
| PROC_TRIGIN | Debug pin | I | CMOS | SE | S-Processor Line |
| PROC_TRIGOUT | Debug pin | O | CMOS | SE | S-Processor Line |
| DRAM_RESET# | Memory Reset | O | CMOS | SE | H-Processor Line P-Processor Line U-Processor Line |