| Operating Voltage | Voltage Range for Processor Operating Mode | P/U-Processor Line | 0 | — | 1.6 | V | 1,2,3, 7,12,15 |
| Operating Voltage | Voltage Range for Processor Operating Mode | S- Processor Line | 0 | — | 1.72 | V | 1,2,3, 7,12,15 |
| IccMAX (H Processor) | Maximum Processor ICC | H-Processor Line (45W) 6+8/ 6+4 -Core | — | — | 160 | A | 4,5,6,7,11 |
| IccMAX (H Processor) | Maximum Processor ICC | H-Processor Line (45W) 4+8/4+4 -Core | — | — | 120 | A | 4,5,6,7,11 |
| IccMAX (P Processor) | Maximum Processor ICC | P-Processor Line (28W) 6+8 -Core | — | — | 109 | A | 4,5,6,7,11 |
| IccMAX (P Processor) | Maximum Processor ICC | P-Processor Line (28W) 4+8 -Core | — | — | 85 | A | 4,5,6,7,11 |
| IccMAX (U15 Processor) | Maximum Processor ICC | U-Processor Line (15W) | — | — | 80 | A | 4,5,6,7,11 |
| IccMAX (U9 Processor) | Maximum Processor ICC | U-Processor Line (9W) | — | — | 50 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (125W) 8+4 -Core | — | — | 240 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (125W) 6+4 -Core | — | — | 175 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (125W) 8+8 -Core | — | — | 280 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (65W) 8+8 -Core | — | — | 240 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (65W) 8+4-Core | — | — | 220 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (35W) 8+8 -Core | — | — | 154 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (35W) 8+4 -Core | — | — | 145 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (65W) 6+0 -Core | — | — | 175 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (60W/58W) 4+0 -Core | — | — | 110 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (35W) 6+0 -Core | — | — | 100 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (35W) 4+0 -Core | — | — | 90 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (35W) 2+0 -Core | — | — | 37 | A | 4,5,6,7,11 |
| IccMAX (S Processor) | Maximum Processor ICC | S-Processor Line (46W) 2+0 -Core | — | — | 49 | A | 4,5,6,7,11 |
| IccTDC | Thermal Design Current (TDC) for processor VccCORE Rail | — | — | — | VR_TDC | A | 9 |
| TOBVCC | DC Tolerance | PS0, PS1 ,PS2, PS3 | — | — | ±20 | mV | 3, 6, 8 |
| TOBVCC+Ripple | Total Tolerance | PS0, PS1, PS2, PS3 | — | — | -35 /+50 | mV | 3, 6, 8,16 |
| DC_LL | Loadline slope within the VR regulation loop capability | H-Processor Line 4+8/4+4 (45W) | 0 | — | 2.3 | mΩ | 10,13,14 |
| DC_LL | Loadline slope within the VR regulation loop capability | H-Processor Line 6+8/6+4 (45W) | 0 | — | 2.3 | mΩ | 10,13,14 |
| DC_LL | Loadline slope within the VR regulation loop capability | P-Processor Line 6+8 (28W) | 0 | — | 2.3 | mΩ | 10,13,14 |
| DC_LL | Loadline slope within the VR regulation loop capability | P-Processor Line 4+8 (28W) | 0 | — | 2.3 | mΩ | 10,13,14 |
| DC_LL | Loadline slope within the VR regulation loop capability | U-Processor Line (15W) | 0 | — | 2.8 | mΩ | 10,13,14 |
| DC_LL | Loadline slope within the VR regulation loop capability | U-Processor Line (9W) | 0 | — | 4.5 | mΩ | 10,13,14 |
| DC_LL | Loadline slope within the VR regulation loop capability | S-Processor Line 8+ 8/8+4 Core (125W) | 0 | — | 1.1 | mΩ | 10,13,14 |
| S-Processor Line 6+4 Core ( 125W) | 0 | — | 1.7 | mΩ | 10,13,14 |
| DC_LL | Loadline slope within the VR regulation loop capability | S-Processor Line 8+ 8 Core (65W) | 0 | — | 1.1 | mΩ | 10,13,14 |
| S-Processor Line 8+ 8 Core (35W) | 0 | — | 1.7 | mΩ | 10,13,14 |
| S-Processor Line 6+ 0 Core (65W/35W) | 0 | — | 1.7 | mΩ | 10,13,14 |
| S-Processor Line 4+ 0 Core | 0 | — | 1.7 | mΩ | 10,13,14 |
| S-Processor Line 2+ 0 Core | 0 | — | 1.7 | mΩ | 10,13,14 |
| S-Processor Line 8+ 4 Core (65W) | 0 | — | 1.1 | mΩ | 10,13,14 |
| S-Processor Line 8+ 4 Core (35W) | 0 | — | 1.7 | mΩ | 10,13,14 |
| AC_LL | AC Loadline 3 | P-Processor Line 6+8 (28W) | — | — | - Below 400kHz:2.3
- 400kHz-2MHz:linear decrease with log (frequency) from 2.3 to 1.9
- Above 2MHz: 1.9
| mΩ | 10,13,14 |
| P-Processor Line 4+8 (28W) |
| U-Processor Line (15W) | | | - Below 400kHz: 2.8
- 400kHz-2MHz: linear decrease with log (frequency) from 2.8 to 2.2
- Above 2MHz: 2.2
|
| AC Loadline 3 | U -Processor Line (9W) | — | — | Same as DC LL | mΩ | 10,13,14 |
| AC_LL | AC Loadline 3 | H-Processor Line (45W) | — | — | - Below 400kHz:2.3
- 400kHz-2MHz:linear decrease with log (frequency) from 2.3 to 1.9
- Above 2MHz: 1.9
| mΩ | 10,13,14 |
| AC_LL | AC Loadline 3 | S Processor Line | 0 | — | Same as DC LL | mΩ | 10,13,14 |
| T_OVS_TDP_MAX | Maximum Overshoot time TDP/virus mode | — | — | — | 500 | μs | |
| V_OVS TDP_MAX/virus_MAX | Maximum Overshoot at TDP/virus mode | — | — | — | 10 | % | |
- All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
- Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel Speed-step Technology, or low-power states).
- The voltage specification requirements are measured across Vcc_SENSE and Vss_SENSE as near as possible to the processor. The measurement needs to be performed with a 20MHz bandwidth limit on the oscilloscope, 1.5pF maximum probe capacitance, and 1Ω minimum impedance. The maximum length of the ground wire on the probe should be less than 5mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
- Processor VccCORE VR to be designed to electrically support this current.
- Processor VccCORE VR to be designed to thermally support this current indefinitely.
- Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated.
- Long term reliability cannot be assured in conditions above or below Maximum/Minimum functional limits.
- PSx refers to the voltage regulator power state as set by the SVID protocol.
- Refer to Intel Platform Design Studio (iPDS) for the minimum, typical, and maximum VCC allowed for a given current and Thermal Design Current (TDC).
- LL measured at sense points.
- Typ column represents IccMAX for commercial application it is NOT a specification - it's a characterization of limited samples using limited set of benchmarks that can be exceeded.
- Operating voltage range in steady state.
- LL spec values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
- Load Line (DC) should be measured by the VRTT tool and programmed accordingly via the BIOS Load Line override setup options. DC Load Line BIOS programming directly affects power measurements (DC).
- An IMVP9.1 controller to support VccCORE need to have an offset voltage capability and potentially VccCORE output voltage (VID+Offset) may be higher than 1.5V.
- Ripple can be higher if DC TOB is below 20mV, as long as Total TOB is within -35mV/+50mV.
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