| DDR0_DQ[1:0][7:0] DDR1_DQ[1:0][7:0] DDR2_DQ[1:0][7:0] DDR3_DQ[1:0][7:0] DDR4_DQ[1:0][7:0] DDR5_DQ[1:0][7:0] DDR6_DQ[1:0][7:0] DDR7_DQ[1:0][7:0] | Data Buses: Data signals interface to the SDRAM data buses. Example: DDR0_DQ1[5] refers to DDR channel 0, Byte 1, Bit 5. | I/O | LP4x-LP5 | SE | P Processor Line U Processor Line H Processor Line |
| DDR0_DQSP[1:0] DDR1_DQSP[1:0] DDR2_DQSP[1:0] DDR3_DQSP[1:0] DDR4_DQSP[1:0] DDR5_DQSP[1:0] DDR6_DQSP[1:0] DDR7_DQSP[1:0] DDR0_DQSN[1:0] DDR1_DQSN[1:0] DDR2_DQSN[1:0] DDR3_DQSN[1:0] DDR4_DQSN[1:0] DDR5_DQSN[1:0] DDR6_DQSN[1:0] DDR7_DQSN[1:0] | Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions. | I/O | LP4x-LP5 | Diff | P Processor Line U Processor Line H Processor Line |
| DDR0_CLK_N DDR0_CLK_P DDR1_CLK_N DDR1_CLK_P DDR2_CLK_N DDR2_CLK_P DDR3_CLK_N DDR3_CLK_P DDR4_CLK_N DDR4_CLK_P DDR5_CLK_N DDR5_CLK_P DDR6_CLK_N DDR6_CLK_P DDR7_CLK_N DDR7_CLK_P | SDRAM Differential Clock: Differential clocks signal pairs, pair per channel and package. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM. | I/O | LP4x-LP5 | Diff | P Processor Line U Processor Line H Processor Line |
| DDR0_CKE[1:0] DDR1_CKE[1:0] DDR2_CKE[1:0] DDR3_CKE[1:0] DDR4_CKE[1:0] DDR5_CKE[1:0] DDR6_CKE[1:0] DDR7_CKE[1:0] | Clock Enable: (1 per rank) These signals are used to: | I/O | LP4x-LP5 | SE | P Processor Line U Processor Line H Processor Line |
| DDR0_CS[1:0] DDR1_CS[1:0] DDR2_CS[1:0] DDR3_CS[1:0] DDR4_CS[1:0] DDR5_CS[1:0] DDR6_CS[1:0] DDR7_CS[1:0] | Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank. The Chip select signal is Active High. | I/O | LP4x-LP5 | SE | P Processor Line U Processor Line H Processor Line |
| DDR0_CA[5:0] DDR1_CA[5:0] DDR2_CA[5:0] DDR3_CA[5:0] DDR4_CA[5:0] DDR5_CA[5:0] DDR6_CA[5:0] DDR7_CA[5:0] | Command Address: These signals are used to provide the multiplexed command and address to the SDRAM. | I/O | LP4x-LP5 | SE | P Processor Line U Processor Line H Processor Line |
| DDR0_CA[6] DDR1_CA[6] DDR2_CA[6] DDR3_CA[6] DDR4_CA[6] DDR5_CA[6] DDR6_CA[6] DDR7_CA[6] | Command Address: These signals are used to provide the multiplexed command and address to the SDRAM. | I/O | LP5 | SE | P Processor Line U Processor Line H Processor Line |
| DDR[7:0]_WCK_P DDR[7:0]_WCK_N | Write Clocks: WCK_N and WCK_P are differential clocks used for WRITE data capture and READ data output. | O | LP5 | Diff | P Processor Line U Processor Line H Processor Line |
| DDR_COMP DDR_RCOMP | System Memory Resistance Compensation | A | A | SE | P Processor Line U Processor Line H Processor Line |
| DRAM_RESET# | Memory Reset | O | CMOS | SE | P Processor Line U Processor Line H Processor Line |