The PECI interface operates at a nominal voltage set by Vcc1p05_PROC. The set of DC electrical specifications shown in the following table is used with devices normally operating from a Vcc1P05_PROC interface supply.
Vcc1p05_PROC nominal levels will vary between processor families. All PECI devices will operate at the Vcc1p05_PROC level determined by the processor installed in the system.
PECI DC Electrical Limits
Definition and Conditions
Internal pull up resistance
Input Voltage Range
0.1 * Vcc1p05_PROC
Input Voltage Low- Edge Threshold Voltage
0.275 * Vcc1p05_PROC
Input Voltage High- Edge Threshold Voltage
0.550 * Vcc1p05_PROC
Bus Capacitance per Node
leakage current @ 0 V
leakage current @ Vcc1p05
Vcc1p05_PROC supplies the PECI interface. PECI behavior does not affect Vcc1p05_PROC minimum / maximum specifications.
The leakage specification applies to powered devices on the PECI bus.
The PECI buffer internal pull up resistance measured at 0.75* Vcc1p05_PROC.
Input Device Hysteresis
The input buffers in both client and host models should use a Schmitt-triggered input design for improved noise immunity. Use the following figure as a guide for input buffer design.