Enabling the Timers

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Revision History
Introduction and SKU Definition
PCH Controller Device IDs
- Device and Revision ID Table
Memory Mapping
- Functional Description
- Memory Map
  - Boot Block Update Scheme
System Management
- Theory of Operation
  - Handling an Intruder
  - TCO Modes
High Precision Event Timer (HPET)
- Features Supported
PCH Thermal Sensor
Power Delivery
- Power and Ground Signals
- FIVR
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
- Timer Programming
- Reading from the Interval Timer
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface eSPI
General Purpose Input and Output (GPIO)
- Signal Description
- Functional Description
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Touch Host Controller (THC)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals
- Signal Description

The BIOS or operating system PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), and interrupt type (to select the edge or level type for each timer).

The Device Driver code should do the following for an available timer:

Set the Overall Enable bit (Offset 10h, bit 0).

Set the timer type field (selects one-shot or periodic).

Set the interrupt enable.

Set the comparator value.

Interrupt Levels

Periodic Versus Non-Periodic Modes Interrupt Levels