| GPP_D0 / THC0_SPI1_CS# / SBK0 / BK0 | OD | Blink BK 0: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D1 / THC0_SPI1_CLK / SBK1 / BK1 | OD | Blink BK 1: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D2 / THC0_SPI1_IO1 / SBK2 / BK2 | OD | Blink BK 2: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D3 / THC0_SPI1_IO0 / SBK3 / BK3 | OD | Blink BK 3: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_C6 / ISH_I2C2_SDA / I2C3_SDA / SBK4 / BK4 | OD | Blink BK 4: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_G2 / DNX_FORCE_RELOAD | I | Download and Execute (DnX):Intel® CSME ROM samples this pin any time ROM begins execution. This includes the following conditions: - G3 Exit.
- Sx, Moff Exit.
- Cold Reset(Host Reset with Power Cycle) Exit.
- Warm Reset(Host Reset without Power Cycle) Exit if Intel® CSME was shutdown in Warm Reset.
- 0 => No DnX; 1 => Enter DnX mode.
This pin must not be sampled high at the sampling time for normal operation. |
| GPP_F15 / M2_SKT2_CFG0 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_F16 / M2_SKT2_CFG1 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_F17 / M2_SKT2_CFG2 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GGPP_F18 / M2_SKT2_CFG3 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_E0 / SATAXPCIE0 / SATAGP0 | I | SATA port 0 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_E1 / SATAXPCIE1 / SATAGP1 | I | SATA port 1 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_E2 / SATAXPCIE2 / SATAGP2 | I | SATA port 2 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_F0 / SATAXPCIE3 / SATAGP3 | I | SATA port 3 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_F1 / SATAXPCIE4 / SATAGP4 | I | SATA port 4 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_F2 / SATAXPCIE5 / SATAGP5 | I | SATA port 5 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_F3 / SATAXPCIE6 / SATAGP6 | I | SATA port 6 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_F4 / SATAXPCIE7 / SATAGP7 | I | SATA port 7 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_D0 / THC0_SPI1_CS# / SBK0 / BK0 | OD | Serial Blink SBK 0: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D1 / THC0_SPI1_CLK / SBK1 / BK1 | OD | Serial Blink SBK 1: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D2 / THC0_SPI1_IO1 / SBK2 / BK2 | OD | Serial Blink SBK 2: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D3 / THC0_SPI1_IO0 / SBK3 / BK3 | OD | Serial Blink SBK 3: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_C6 / ISH_I2C2_SDA / I2C3_SDA / SBK4 / BK4 | OD | Serial Blink SBK 4: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_G13 / DDP1_CTRLDATA / TBT_LSX0_RXD / BSSB_LS0_TX | I/O | ThunderboltTM Low Speed Controller Receiver Data 0 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_G12 / DDP1_CTRLCLK / TBT_LSX0_TXD / BSSB_LS0_RX | I/O | Thunderbolt Low Speed Controller Transmit Data 0 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_G15 / DDP2_CTRLDATA / TBT_LSX1_RXD / BSSB_LS1_TX | I/O | Thunderbolt Low Speed Controller Receiver Data 1 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_G14 / DDP2_CTRLCLK / TBT_LSX1_TXD / BSSB_LS1_RX | I/O | Thunderbolt Low Speed Controller Transmit Data 1 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_G9 / ISH_SPI_CLK / DDP3_CTRLDATA / GSPI2_CLK / TBT_LSX2_RXD / BSSB_LS2_TX | I/O | Thunderbolt Low Speed Controller Receiver Data 2 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_G8 / ISH_SPI_CS# / DDP3_CTRLCLK / GSPI2_CS0# / TBT_LSX2_TXD / BSSB_LS2_RX | I/O | Thunderbolt Low Speed Controller Transmit Data 2 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_G11 / ISH_SPI_MOSI / DDP4_CTRLDATA / GSPI2_MOSI / TBT_LSX3_RXD / BSSB_LS3_TX | I/O | Thunderbolt Low Speed Controller Receiver Data 3 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_G10 / ISH_SPI_MISO / DDP4_CTRLCLK / GSPI2_MISO / TBT_LSX3_TXD / BSSB_LS3_RX | I/O | Thunderbolt Low Speed Controller Transmit Data 3 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_H23 / TIME_SYNC0 | I | Time Synchronization GPIO 0: Timed GPIO event for time synchronization for interfaces that do not support time synchronization natively. |
| GPP_B1 / GSPI1_CS1# / TIME_SYNC1 | I | Time Synchronization GPIO 1: Timed GPIO event for time synchronization for interfaces that do not support time synchronization natively. |