PCI Express* Port Support Feature Details

Intel® 500 Series Chipset Family PCH Datasheet Volume 1

ID	Date	Version	Classification
635218	30/09/2021 00:00:00	006	Public Content

PCH	Max Transfer Rate	Max Device (Ports)	Max Lanes	PCIe* Gen Type	Encoding	Transfer Rate (MT/s)		Theoretical Max Bandwidth (GB/s)
							x1	x2	x4
PCH-H	8 GT/s (Gen3)	16	24	1	8b/10b	2500	0.25	0.50	1.00
				2	8b/10b	5000	0.50	1.00	2.00
				3	128b/130b	8000	1.00	2.00	3.94
Notes: Theoretical Maximum Bandwidth (GB/s) = ((Transfer Rate * Encoding * # PCIe Lanes) /8)/1000 Gen3 Example: = ((8000 * 128/130* 4)/8)/1000 = 3.94 GB/s When GbE is enabled on a PCIe* Root Port, the Max. Device (Ports) value listed is reduced by a factor of 1

Notes:

The PCH PCIe* Link Configuration support will vary depending on the PCH SKU. Refer to the PCH SKU details covered in the "Introduction" section

RP# refers to a specific PCH PCI Express* Root Port #; for example RP3 = PCH PCI Express* Root Port 3

A PCIe* Lane is composed of a single pair of Transmit (TX) and Receive (RX) differential pairs, for a total of four data wires per PCIe* Lane (such as, PCIE[3]_TXP/ PCIE[3]_TXN and PCIE[3]_RXP/ PCIE[3]_RXN make up PCIe Lane 3). A connection between two PCIe* devices is known as a PCIe* Link, and is built up from a collection of one or more PCIe* Lanes which make up the width of the link (such as bundling 2 PCIe* Lanes together would make a x2 PCIe* Link). A PCIe* Link is addressed by the lowest number PCIe* Lane it connects to and is known as the PCIe* Root Port (such as a x2 PCIe* Link connected to PCIe* Lanes 3 and 4 would be called x2 PCIe* Root Port 3).

The PCIe* Lanes can be configured independently from one another but the max number of configured Root Ports (Devices) must not be exceeded
- PCH-H: A maximum of 16 PCIe* Root Ports (or devices) can be enabled
- When a GbE Port is enabled, the maximum number of PCIe* Ports (or devices) that can be enabled reduces based off the following:
  - PCH-H: Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)

Unidentified lanes within a PCIe* Link Configuration are disabled but their physical lanes are used for the identified Root Port

Supports Remapped (Intel® Rapid Storage Technology) PCIe* Storage Devices
- Specific PCIe* lanes can be used for a x2 or x4 Intel® Rapid Storage Technology Remapped PCIe* NVMe SSD or a x2 or x4 Next Generation Intel® Optane™ Memory Device
- Not all PCH PCIe* lanes support Intel® RST for PCIe* Storage Devices. Refer to the PCH SKU details covered in the "Introduction" section for specific PCH SKU PCIe* lane support

Lane Reversal Supported Motherboard PCIe* Configurations = 1x4, 2x1+1x2, and 2x2
- The 2x1+1x2 configuration is enabled by setting the PCIe* Controller soft straps to 1x2+2x1 with Lane Reversal Enabled
- 1x4 = 1x4 with Lane Reversal Disabled, 1x4 LR = 1x4 with Lane Reversal Enabled
- 2x2 = 2x2 with Lane Reversal Disabled, 2x2 LR = 2x2 with Lane Reversal Enabled

Un-used USB 3.2/PCIe and SATA/PCIe Combo Port Lanes must be statically assigned to "PCIe, SATA, or USB3" through their Combo Port Soft Straps discussed in the SPI Programming Guide using the Intel Flash Image Tool (FIT).