Intel® 500 Series Chipset Family PCH Datasheet Volume 1

Datasheet

ID Date Version Classification
635218 30/09/2021 00:00:00 006 Public Content
Document Table of Contents
ICC

WAIT States from eSPI Slave

There are situations when the slave cannot predict the length of the command packet from the master (PCH). For non-posted transactions, the slave is allowed to respond with a limited number of WAIT states.

A WAIT state is a 1-byte response code. They must be the first set of response byte from the slave after the TAR cycles.