Functional Description

Legal Disclaimer
Revision History
Introduction and SKU Definition
PCH Controller Device IDs
- Device and Revision ID Table
Memory Mapping
- Functional Description
- Memory Map
  - Boot Block Update Scheme
System Management
- Theory of Operation
  - Handling an Intruder
  - TCO Modes
High Precision Event Timer (HPET)
- Features Supported
PCH Thermal Sensor
Power Delivery
- Power and Ground Signals
- FIVR
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
- Timer Programming
- Reading from the Interval Timer
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface eSPI
General Purpose Input and Output (GPIO)
- Signal Description
- Functional Description
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Touch Host Controller (THC)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals
- Signal Description

The PCH provides an System Management Bus (SMBus) 2.0 host controller as well as an SMBus Slave Interface.

Host Controller: Provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The PCH is also capable of operating in a mode in which it can communicate with I²C compatible devices.

Slave Interface: Allows an external master to read from or write to the PCH. Write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. The PCH’s internal host controller cannot access the PCH’s internal Slave Interface.

I/O Signal Planes and States Host Controller