Intel® Core™ Ultra 200S, Intel® Core™ Ultra 200S Plus ,Intel® Core™ Ultra 200HX and 200HX Plus Series Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
832586 03/17/2026 Public
Document Table of Contents
LAM

Fan Speed Control Scheme with DTS

With Digital Thermal Sensor (DTS) 1.1

To correctly use DTS 1.1, the designer must first select a worst case scenario TAMBIENT, and ensure that the Fan Speed Control (FSC) can provide a Ψ CA that is equivalent or greater than the Ψ CA specification.

The DTS 1.1 implementation consists of two points:

  • a Ψ CA at T CONTROL
  • a Ψ CA at DTS = -1

  • The Ψ CA point at DTS = -1 defines the minimum Ψ CA required at Processor Base Power considering the worst case system design T AMBIENT design point:

    Ψ CA = (T CASE-MAX - T AMBIENT-TARGET - 1 ) / Processor Base Power

    For example, for a 125 W Processor Base Power part, the T CASE maximum is 62.0 °C and at a worst case design point of 40 °C local ambient this will result in:

    Ψ CA = (62.0 - 40 - 1) / 125 = 0.168 °C/W

    Similarly for a system with a design target of 45 °C ambient, the Ψ CA at DTS = -1 needed will be 0.128 °C/W.

  • The second point defines the thermal solution performance (Ψ CA ) at T CONTROL . The following table lists the required Ψ CA for the various Processor Base Power processors.

These two points define the operational limits for the processor for DTS 1.1 implementation. At T CONTROL the fan speed must be programmed such that the resulting Ψ CA is better than or equivalent to the required Ψ CA listed in the following table. Similarly, the fan speed should be set at DTS = -1 such that the thermal solution performance is better than or equivalent to the ΨCA requirements at T AMBIENT-MAX .

The fan speed controller must linearly ramp the fan speed from processor DTS = T CONTROL to processor DTS = -1.

Digital Thermal Sensor (DTS) 1.1 Definition Points

Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above TCONTROL

Segment and Package Processor IA Cores, Graphics, Configuration and Processor Base Power

PCG7

ΨCA at DTS = TCONTROL 1, 2 At System TAMBIENT_​MAX = 30 °C ΨCA at DTS = -1 At System TAMBIENT_​MAX = 40 °C ΨCA at DTS = -1 At System TAMBIENT_​MAX = 45 °C ΨCA at DTS = -1 At System TAMBIENT_​MAX = 50 °C
S-Processor Line LGA 8P+16E Core 125W

2020A

0.26 0.30 0.25 0.20
8P+12E Core 125W

2020A

0.28 0.23 0.18 0.13
6P+8E Core 125W

2020A

0.29 0.18 0.14 0.10
8P+16E Core 65W

2022C

0.63 0.72 0.64 0.55
8P+12E Core 65W

2022C

0.68 0.65 0.56 0.48
6P+8E Core 65W

2022C

0.68 0.55 0.47 0.38
6P+4E Core 65W

2022C

0.69 0.61 0.53 0.44
8P+16E Core 35W

2022D

1.01 1.59 1.44 1.29
8P+12E Core 35W

2022D

1.00 1.55 1.40 1.24
6P+8E Core 35W

2022D

1.01 1.43 1.28 1.13
6P+4E Core 35W

2022D

0.99 1.36 1.21 1.05
S-Plus Processor Line LGA 8P+16E Core 125W

2020A

0.26 0.30 0.25 0.20
6P+12E Core 125W

2020A

0.28 0.23 0.18 0.13
Notes:
  1. ΨCA at “DTS = TCONTROL” is applicable to systems that have an internal TRISE (TROOM temperature to Processor cooling fan inlet) of less than 10 °C. In case the expected TRISE is greater than 10 °C, a correction factor should be used as explained below. For each 1 °C TRISE above 10 °C, the correction factor (CF) is defined as CF = 1.7 / (Processor Base Power).
  2. The table data match for GT0.

With Digital Thermal Sensor (DTS) 2.0

To simplify processor thermal specification compliance, the processor calculates the DTS Thermal Profile from TCONTROL Offset, TCC Activation Temperature, Processor Base Power, and the Thermal Margin Slope provided in the following table.

Note:TCC Activation Offset is 0 for the processors.

Using the DTS Thermal Profile, the processor can calculate and report the Thermal Margin, where a value less than 0 indicates that the processor needs additional cooling, and a value greater than 0 indicates that the processor is sufficiently cooled.

Digital Thermal Sensor (DTS) 2.0 Definition Points

Thermal Margin Slope

Segment and Package Processor IA Cores, Graphics, Configuration and Processor Base Power PCG Temperature Control Offset TCC Activation [°C] Thermal Margin Slope [°C/W]
S-Processor Line LGA 8P+16E Core 125W

2020A

20 105 0.390
8P+12E Core 125W

2020A

20 105 0.450
6P+8E Core 125W

2020A

20 105 0.480
8P+16E Core 65W

2022C

20 105 0.700
8P+12E Core 65W

2022C

20 90 0.606
6P+8E Core 65W

2022C

20 105 0.860
6P+4E Core 65W

2022C

20 105 0.800
8P+16E Core 35W

2022D

30 105 0.820
8P+12E Core 35W

2022D

29 105 0.850
6P+8E Core 35W

2022D

25 105 1.950
6P+4E Core 35W

2022D

23 105 1.020
S-Plus Processor Line LGA 8P+16E Core 125W

2020A

20 105 0.390
6P+12E Core 125W

2020A

20 105 0.450
S-Plus Processor Line LGA 8P+12E Core 125W

2020A

20 105 0.450
8P+8E Core 125W

2020A

TBD TBD TBD
6P+8E Core 125W

2020A

20 105 0.480
Notes:
  1. The default BIOS settings for this SKU is 10C TCC offset.