Fixed I/O Address Ranges
The following table shows the Fixed I/O decode ranges from the processor perspective. For each I/O range, there may be separate behavior for reads and writes.
I/O cycles that go to target ranges that are marked as Reserved will be handled as follow : writes are ignored and reads will return all 1's. The P2SB will claim many of the fixed I/O accesses and forward those transactions over IOSF-SB to their functional target.
Address ranges that are not listed or marked Reserved are NOT positively decoded (unless assigned to one of the variable ranges) and will be internally terminated.
Fixed I/O Ranges Decoded by Processor
| I/O Address | Read Target | Write Target | Internal Unit (Unless[E]: External)2 | Separate Enable/Disable |
|---|
| 20h – 21h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 24h – 25h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 28h – 29h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 2Ch – 2Dh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 30h – 31h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 34h – 35h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 38h – 39h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 3Ch – 3Dh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 40h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 42h-43h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 50h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 52h-53h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 61h | NMI Controller | NMI Controller | CPU I/F | None |
| 63h | NMI Controller 1 | NMI Controller 1 | CPU I/F | Yes, alias to 61h. GIC.P61AE |
| 65h | NMI Controller 1 | NMI Controller 1 | CPU I/F | Yes, alias to 61h. GIC.P61AE |
| 67h | NMI Controller 1 | NMI Controller 1 | CPU I/F | Yes, alias to 61h. GIC.P61AE |
| 70h | RTC Controller | NMI and RTC Controller | RTC | None |
| 80h3 | eSPI or PCIe | eSPI or PCIe | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 84h - 86h | eSPI or PCIe | eSPI or PCIe | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 88h | eSPI or PCIe | eSPI or PCIe | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 8Ch - 8Eh | eSPI or PCIe | eSPI or PCIe | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 92h | Reset Generator | Reset Generator | CPU I/F | None |
| A0h - A1h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| A4h - A5h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| A8h - A9h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| ACh - ADh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| B0h - B1h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| B2h - B3h | Power Management | Power Management | Power Management | None |
| B4h - B5h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| B8h - B9h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| BCh - BDh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 4D0h – 4D1h | Interrupt Controller | Interrupt Controller | Interrupt Controller | None |
| CF9h | Reset Generator | Reset Generator | Interrupt controller | None |
- Only if the Port 61 Alias Enable bit (GIC.P61AE) bit is set. Otherwise, the cycle is internally terminated by the Processor.
- Destination of eSPI when eSPI Disabled pin strap is 0.
- This includes byte, word or double-word (DW) access at I/O address 80h.
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