Signal Description
For more information, refer to Intel® 800 Series Chipset Family Platform Controller Hub (PCH) Datasheet, Volume 1 of 2 (#833778 )
| Signal Name | Type | Description |
|---|
| PLT_PWROK | I | Platform Power OK: When asserted, PLT_PWROK is an indication to the processor that all of its core power rails have been stable. The platform may drive asynchronously. When PLT_PWROK is de-asserted, the processor asserts PLTRST#. - PLT_PWROK must not glitch, even if RSMRST# is low
- An external pull-down resistor is required.
|
| RSMRST# | I | Primary Well Reset: This signal is used for resetting the primary power plane logic. This signal must be asserted for at least 10ms before de-asserting. An external pull down resistor is required. |
| SLP_S0# | O | S0 Sleep Control: When the processor is in C10 state, this pin will assert to indicate VR controller can go into a light load mode. This signal can also be connected to EC for other power management related optimizations. An external pull-up resistor is required. |
| GPP_SD00/TIME_SYNC0 GPP_SD01/TIME_SYNC1 | I | Time Synchronization: Used for synchronization both input (latch time when pin asserted) and output (toggle pin when programmed time is hit). |
| PS_ON# | O | Used to indicate to PSU when to turn off its main rails |
| RESET_SYNC# | I/O | Bidirectional signal used to synchronize reset events between the processor and PCH. Sync reset exits with the PCH in following two steps: -
The processor floats the RESET_SYNC# pin to allow it to be pulled high by the platform - The processor waits until it sees the RESET_SYNC# pin go high before proceeding to reset exit.
The PCH will stop driving the pin low when the eSPI controller in the PCH is out of reset and ready to receive traffic over the eSPI link. It is required that the PCH eSPI controller is ready before the processor eSPI controller is released from reset. |
| PROC_C10_GATE# | O | When asserted, PROC_C10_GATE# is the indication to the system that the processor is entering C10 and can handle the voltages on the VCCPRIM_IO and VCCPRIM_VNNAON rails being lowered to 0 V. When de-asserted must ramp back up to their operational voltage levels. The power good indicators for these rails must still be asserted high when these rails are lowered to 0 V during PROC_C10_GATE# assertion and while these rails ramp back up to their operational levels after PROC_C10_GATE# de-assertion. |