Processor Configuration Register Definitions and Address Ranges
This chapter describes the processor configuration register, I/O, memory address ranges and Model Specific Registers (MSRs). The chapter provides register terminology. PCI Devices and Functions are described.
Register Terminology
Table below lists the register-related terminology and access attributes that are used in this document. Register Attribute Modifiers table provides the attribute modifiers.
| Item | Description |
|---|---|
| RO | Read Only: These bits can only be read by software, writes have no effect. The value of the bits is determined by the hardware only. |
| RW | Read / Write: These bits can be read and written by software. |
| RW1C | Read / Write 1 to Clear: These bits can be read and cleared by software. Writing a '1' to a bit will clear it, while writing a '0' to a bit has no effect. Hardware sets these bits. |
| RW0C | Read / Write 0 to Clear: These bits can be read and cleared by software. Writing a '0' to a bit will clear it, while writing a '1' to a bit has no effect. Hardware sets these bits. |
| RW1S | Read / Write 1 to Set: These bits can be read and set by software. Writing a '1' to a bit will set it, while writing a '0' to a bit has no effect. Hardware clears these bits. |
| RsvdP | Reserved and Preserved: These bits are reserved for future RW implementations and their value should not be modified by software. When writing to these bits, software should preserve the value read. When SW updates a register that has RsvdP fields, it should read the register value first so that the appropriate merge between the RsvdP and updated fields will occur. |
| RsvdZ | Reserved and Zero: These bits are reserved for future RW1C implementations. Software should use 0 for writes. |
| WO | Write Only: These bits can only be written by software, reads return zero. |
| RC | Read Clear: These bits can only be read by software, but a read causes the bits to be cleared. Hardware sets these bits. |
| RSW1C | Read Set / Write 1 to Clear: These bits can be read and cleared by software. Reading a bit will set the bit to '1'. Writing a '1' to a bit will clear it, while writing a '0' to a bit has no effect. |
| RCW | Read Clear / Write: These bits can be read and written by software, but a read causes the bits to be cleared. |
| Attribute Modifier | Applicable Attribute | Description |
|---|---|---|
| S | RO (w/ -V) | Sticky: These bits are only re-initialized to their default value by a “Power Good Reset” (Cold Reset). |
| RW | ||
| RW1C | ||
| RW1S | ||
| -K | RW | Key: These bits control the ability to write other bits (identified with a 'Lock' modifier) |
| -L | RW | Lock: Hardware can make these bits “Read Only” using a separate configuration bit or other logic. |
| WO | ||
| -O | RW | Once: After reset, these bits can only be written by software once, after which they become “Read Only”. |
| WO | ||
| -FW | RO | Firmware Write: The value of these bits can be updated by processor hardware mechanisms that may be firmware dependent. |
| -V | RO | Variant: The value of these bits can be updated by hardware. |
PCI Devices and Functions
The processor contains multiple PCI devices. The configuration registers for these devices are mapped as devices residing on PCI Bus 0.
·Device 0: Host Bridge / DRAM Controller / LLC Controller 0 – Logically this device appears as a PCI device residing on PCI bus 0. Device 0 contains the standard PCI header registers, PCI Express base address register, DRAM control (including thermal/throttling control), configuration for the DMI, and other processor specific registers.
·Device 2: Processor Graphics – Logically, this device appears as a PCI device residing on PCI Bus 0. Device 2 contains the configuration registers for 3D, 2D, and display functions. I
·Device 4: Dynamic Tuning Technology (DTT) - Logically, this device appears as a PCI device residing on PCI Bus 0. Device 4 contains the configuration registers for the DPPM device.
·Device 5: Image Processing Unit (IPU) – Logically, this device appears as a PCI device residing on PCI Bus 0. Device 5 contains the configuration registers for the Image Processing Unit Device.
·Device 10: Crash Log & Telemetry Device – Logically, this device appears as a PCI device residing on PCI Bus 0. Device 10 contains the configuration registers for the Crash Log Device.
·Device 11: Visual Processing Unit – Logically, this device appears as a PCI device residing on PCI Bus 0. Device 11 contains the configuration registers for the Visual Processing Unit
·Device 14: Intel® Volume Management Device. Logically, this device appears as a PCI device residing on PCI Bus 0. Device 14 contains the configuration registers for the Volume Management Device.
| Description | Device | Function |
|---|---|---|
| HOST and DRAM Controller | 0 | 0 |
| Processor Graphics | 2 | 0 |
| Dynamic Tuning Technology | 4 | 0 |
| Image Processing Unit | 5 | 0 |
| Crash Log & Telemetry | 10 | 0 |
| Visual Processing Unit | 11 | 0 |
| Volume Management Device | 14 | 0 |
From a configuration standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0.
System Address Map
The processor supports up to 4TB (42-bits) of address memory space
This section focuses on how the memory space is partitioned and how the separate memory regions are used. I/O address space has simpler mapping and is explained towards the end of this chapter.
The processor supports PCIe port upper prefetchable base/limit registers. This allows the PCIe bridges to claim Memory Mapped I/O (MMIO) accesses above 32 bit. Addressing of greater than 4 GB is allowed on both the DMI Interface or PCIe interfaces. DRAM capacity is limited by the number of address pins available. There is no hardware lock to prevent more memory from being inserted than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the DMI Interface. The exception to this rule is VGA ranges, which may be mapped to PCI Express*, DMI, or to the Processor Graphics device (Processor Graphics). The processor does not remap APIC or any other memory spaces above TOLUD (Top of Low Usable DRAM). The TOLUD register is set to the appropriate value by BIOS. The remapbase/remaplimit registers remap logical accesses bound for addresses above 4GB onto physical addresses that fall within DRAM.
The Address Map includes a number of programmable ranges that are not configured using standard PCI BAR configuration:
·Device 0:
MCHBAR – Host Memory Mapped Configuration (memory subsystem and power management registers). (128 KB window)
VTDPVC0BAR - Memory mapped range for VT-d configuration
REGBAR - Memory mapped range for System Agent registers (16MB window).
GGC.GMS – Graphics Mode Select. Main memory that is pre-allocated to support the Processor Graphics device in VGA (non-linear) and Native (linear) modes – also known as Gfx Data Stolen Memory (GDSM). (0 – 512 MB options). 64MB is the recommended size.
GTT Graphics Memory Size. Main memory that is pre-allocated to support the Processor Graphics Translation Table. (8MB).
·For all other PCI devices within the processor that expose PCI configuration space, the behavior is according to PCI specification.
The rules for the above programmable ranges are:
·For security reasons, the processor positively decodes (FFE0_0000h to FFFF_FFFFh) to DMI. This ensures the boot vector and BIOS execute off the PCH.
·ALL of these ranges should be unique and NON-OVERLAPPING. It is the BIOS or system designer's responsibility to limit memory population so that adequate PCI, PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory space can be allocated.
·In the case of overlapping ranges with memory, the memory decode will be given priority. This is an Intel® Trusted Execution Technology (Intel® TXT) requirement. It is necessary to get Intel® TXT protection checks, avoiding potential attacks.
·There are NO Hardware Interlocks to prevent problems in the case of overlapping memory ranges.
·Accesses to overlapped ranges may produce indeterminate results.
·Peer-to-peer write cycles are allowed below the Top of Low Usable memory (register TOLUD) for DMI Interface to PCI Express VGA range writes. Peer-to-peer cycles to the Processor Graphics VGA range are not supported.
System Address Range Example
DOS Legacy Address Range
The memory address range from 0 to 1 MB is known as Legacy Address. This area is divided into the following address regions:
- 0 – 640 KB - DOS Area
- 640 – 768 KB - Legacy Video Buffer Area
- 768 – 896 KB in 16 KB sections (total of 8 sections) – Expansion Area
- 896 – 960 KB in 16 KB sections (total of 4 sections) – Extended System BIOS Area
- 960 KB – 1 MB Memory, System BIOS Area
The area between 768 KB – 1 MB is also collectively referred to as PAM (Programmable Address Memory). All accesses to the DOS and PAM ranges from any device are sent to DRAM. However, access to the legacy video buffer area is treated differently.
DOS Legacy Address Range
DOS Range (0h – 9_FFFFh)
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main memory.
Legacy Video Area (A_0000h – B_FFFFh)
The same address region is used for both Legacy Video Area.
- Legacy Video Area: The legacy 128 KB VGA memory range, frame buffer, at 000A_0000h – 000B_FFFFh, can be mapped to Processor Graphics (Device 2), to PCI Express (Device 1, 6), and/or to the DMI Interface.
- Monochrome Adapter (MDA) Range: Legacy support for monochrome display adapter
Legacy Video Area
The legacy 128 KB VGA memory range, frame buffer at 000A_0000h – 000B_FFFFh, can be mapped to Processor Graphics (Device 2), to PCI Express (Device 1, 6), and/or to the DMI Interface.
Monochrome Adapter (MDA) Range
Legacy support requires the ability to have a second graphics controller (monochrome) in the system. The monochrome adapter may be mapped to Processor Graphics (Device 2), to PCI Express (Device 1, 6), and/or to the DMI Interface.
Programmable Attribute Map (PAM) (C_0000h – F_FFFFh)
PAM is a legacy BIOS ROM area in MMIO. It is overlaid with DRAM and used as a faster ROM storage area. It has a fixed base address (000C_0000h) and fixed size of 256 KB. The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area. Each section has Read enable and Write enable attributes
NOTE: MTL no longer supports setting READ/Write differently, only both DRAM or both to “DMI” are supported.
PAM Region Space
The PAM registers are mapped in Device 0 configuration space.
- ISA Expansion Area (C_0000h – D_FFFFh)
- Extended System BIOS Area (E_0000h – E_FFFFh)
- System BIOS Area (F_0000h – F_FFFFh)
The processor decodes the Core request, then routes to the appropriate destination (DRAM or DMI).
Snooped accesses from devices to this region are snooped on processor Caches.
Graphics translated requests to this region are not allowed. If such a mapping error occurs, the request will be routed to C_0000h. Writes will have the byte enables de-asserted.
Lower Main Memory Address Range (1 MB – TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the processor (as programmed in the TOLUD register). The processor will route all addresses within this range to the DRAM unless it falls into the optional TSEG, optional ISA Hole or optional Processor Graphics stolen memory.
This address range is divided into two sub-ranges:
- 1 MB to TSEGMB
- TSEGMB to TOULUD
TSEGMB indicates the TSEG Memory Base address.
Main Memory Address Range
ISA Hole (15 MB –16 MB)
MTL does not support the ISA hole being created.
MB to TSEGMB
Processor access to this range will be directed to memory with the exception of the ISA Hole (when enabled).
TSEG
For processor initiated transactions, the processor relies on correct programming of SMM Range Registers (SMRR) to enforce TSEG protection.
TSEG is below Processor Graphics stolen memory, which is at the Top of Low Usable physical memory (TOLUD). BIOS will calculate and program the TSEG BASE in Device 0 (TSEGMB), used to protect this region from DMA access. Calculation is:
TSEGMB = TOLUD – DSM SIZE – GSM SIZE – TSEG SIZE
SMM-mode processor accesses to TSEG always access the physical DRAM.
When the extended SMRAM space is enabled, processor accesses without SMM attribute or without write-back attribute to the TSEG range are handled as invalid accesses.
Non-processor originated accesses such as PCI Express, DMI or processor graphics to enabled SMM space are handled as invalid cycle type with reads and writes to location C_0000h and byte enables turned off for writes.
Protected Memory Range (PMR) - (Programmable)
For robust and secure launch of the MVMM, the MVMM code and private data need to be loaded to a memory region protected from bus master accesses. Support for protected memory region is required for DMA-remapping hardware implementations on platforms supporting Intel® TXT, and is optional for non-Intel® TXT platforms. Since the protected memory region needs to be enabled before the MVMM is launched, hardware should support enabling of the protected memory region independently from enabling the DMA-remapping hardware.
As part of the secure launch process, the SINIT-AC module verifies the protected memory regions are properly configured and enabled. Once launched, the MVMM can setup the initial DMA-remapping structures in protected memory (to ensure they are protected while being setup) before enabling the DMA-remapping hardware units.
To optimally support platform configurations supporting varying amounts of main memory, the protected memory region is defined as two non-overlapping regions:
- Protected Low-memory Region: This is defined as the protected memory region below 4 GB to hold the MVMM code/private data, and the initial DMA-remapping structures that control DMA to host physical addresses below 4 GB. DMA-remapping hardware implementations on platforms supporting Intel® TXT are required to support protected low-memory region 5.
- Protected High-memory Region: This is defined as a variable sized protected memory region above 4 GB, enough to hold the initial DMA-remapping structures for managing DMA accesses to addresses above 4 GB. DMA-remapping hardware implementations on platforms supporting Intel® TXT are required to support protected high-memory region 6, if the platform supports main memory above 4 GB.
Once the protected low/high memory region registers are configured, bus master protection to these regions is enabled through the Protected Memory Enable register. For platforms with multiple DMA-remapping hardware units, each of the DMA-remapping hardware units should be configured with the same protected memory regions and enabled.
DRAM Protected Range (DPR)
This protection range only applies to DMA accesses and GMADR translations. It serves a purpose of providing a memory range that is only accessible to processor streams. The range just below TSEGMB is protected from DMA accesses.
The DPR range works independently of any other range, including the PMRC checks in Intel® VT-d. It occurs post any Intel® VT-d translation. Therefore, incoming cycles are checked against this range after the Intel® VT-d translation and faulted if they hit this protected range, even if they passed the Intel® VT-d translation.
The system will set up:
- 0 to (TSEG_BASE – DPR size – 1) for DMA traffic
- TSEG_BASE to (TSEG_BASE – DPR size) as no DMA.
After some time, software could request more space for not allowing DMA. It will get some more pages and make sure there are no DMA cycles to the new region. DPR size is changed to the new value. When it does this, there should not be any DMA cycles going to DRAM to the new region.
All upstream cycles from 0 to (TSEG_BASE – 1 – DPR size), and not in the legacy holes (VGA), are decoded to DRAM.
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within the system memory address range (< TOLUD) are created for SMM-mode, legacy VGA graphics compatibility, and GFX GTT stolen memory. It is the responsibility of BIOS to properly initialize these regions.
PCI Memory Address Range (TOLUD – 4 GB)
This address range from the top of low usable DRAM (TOLUD) to 4 GB is normally mapped to the DMI Interface, except where other bars override the target to different locations.
PCI Memory Address Range
Upper Main Memory Address Space (4 GB to TOUUD)
The maximum main memory size supported is 64 GB total DRAM memory.
A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger. As a result, TOM and TOUUD registers and REMAPBASE/REMAPLIMIT registers become relevant.
The remap configuration registers exist to remap lost main memory space. The greater than 32-bit remap handling will be handled similar to other MCHs.
Upstream read and write accesses above 39-bit addressing will be treated as invalid cycles by PEG and DMI.
Top of Memory (TOM)
The “Top of Memory” (TOM) register reflects the total amount of populated physical memory. This is NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped IO above TOM).
The TOM was used to allocate the Intel® Management Engine (Intel® ME) stolen memory. The Intel® ME stolen size register reflects the total amount of physical memory stolen by the Intel® ME. The Intel® ME stolen memory is located at the top of physical memory. The Intel® ME stolen memory base is calculated by subtracting the amount of memory stolen by the Intel® ME from TOM.
Top of Upper Usable DRAM (TOUUD)
The Top of Upper Usable DRAM (TOUUD) register reflects the total amount of addressable DRAM. If remap is disabled, TOUUD will reflect TOM minus Intel® ME stolen size. If remap is enabled, then it will reflect the remap limit. When there is more than 4 GB of DRAM and reclaim is enabled, the reclaim base will be the same as TOM minus Intel® ME stolen memory size to the nearest 1 MB alignment.
Top of Low Usable DRAM (TOLUD)
TOLUD register is restricted to 4 GB memory (A[31:20]), but the processor can support up to 64 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD register helps identify the address range between the 4 GB boundary and the top of physical memory. This identifies memory that can be directly accessed (including remap address calculation) that is useful for memory access indication and early path indication. TOLUD can be 1 MB aligned.
TSEG_BASE
The “TSEG_BASE” register reflects the total amount of low addressable DRAM, below TOLUD. BIOS will calculate memory size and program this register; thus, the system agent has knowledge of where (TOLUD) – (Gfx stolen) – (Gfx GTT stolen) – (TSEG) is located. I/O blocks use this minus DPR for upstream DRAM decode.
Memory Re-claim Background
The following are examples of Memory Mapped IO devices that are typically located below 4 GB:
- High BIOS
- TSEG
- GFX stolen
- GTT stolen
- XAPIC
- Local APIC
- MSI Interrupts
- Mbase/Mlimit
- Pmbase/PMlimit
- Memory Mapped IO space that supports only 32B addressing
The processor provides the capability to re-claim the physical memory overlapped by the Memory Mapped IO logical address space. The MCH re-maps physical memory from the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent sized logical address range located just below the Intel® ME stolen memory.
Indirect Accesses to MCHBAR Registers
Similar to prior chipsets, MCHBAR registers can be indirectly accessed using:
Direct MCHBAR access decode:
- Cycle to memory from processor
- Hits MCHBAR base, AND
- MCHBAR is enabled, AND
- Within MMIO space (above and below 4 GB)
GTTMMADR (10000h – 13FFFh) range -> MCHBAR decode
MCHTMBAR -> MCHBAR (Thermal Monitor)
- Cycle to memory from processor, AND
- Targets MCHTMBAR base
IOBAR -> GTTMMADR -> MCHBAR
Memory Remapping
An incoming address (referred to as a logical address) is checked to see if it falls in the memory re-map window. The bottom of the re-map window is defined by the value in the REMAPBASE register. The top of the re-map window is defined by the value in the REMAPLIMIT register. An address that falls within this window is re-mapped to the physical memory starting at the address defined by the TOLUD register. The TOLUD register should be 1 MB aligned.
Hardware Remap Algorithm
The following pseudo-code defines the algorithm used to calculate the DRAM address to be used for a logical address above the top of physical memory made available using re-claiming.
IF (ADDRESS_IN[38:20] >= REMAP_BASE[35:20]) AND
(ADDRESS_IN[38:20] <= REMAP_LIMIT[35:20]) THEN
ADDRESS_OUT[38:20] = (ADDRESS_IN[38:20] - REMAP_BASE[35:20]) +
0000000b & TOLUD[31:20]
ADDRESS_OUT[19:0] = ADDRESS_IN[19:0]
PCI Express* Configuration Address Space
PCIEXBAR is located in Device 0 configuration space. The processor detects memory accesses targeting PCIEXBAR. BIOS should assign this address range such that it will not conflict with any other address ranges.
Graphics Memory Address Ranges
The integrated memory controller can be programmed to direct memory accesses to the Processor Graphics when addresses are within any of the ranges specified using registers in MCH Device 2 configuration space.
- The Graphics Local Memory Register (LMEMBAR) is used to access graphics stolen memory.
- The Graphics Translation Table Base Register (GTTMMADR) is used to access the translation table and graphics control registers.
These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC address ranges. They should reside above the top of memory (TOLUD) and below 4 GB so they do not take any physical DRAM memory space.
Alternatively, these ranges can reside above 4 GB, similar to other BARs that are larger than 32 bits in size.
LMEMBAR is a Prefetchable range in order to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining
Trusted Graphics Ranges
Trusted graphics ranges are NOT supported.
System Management Mode (SMM)
The Core handles all SMM mode transaction routing. The processor does not allow I/O devices access to the CSEG/TSEG/HSEG ranges.
DMI Interface and PCI Express* masters are Not allowed to access the SMM space.
| SMM Space Enabled | Transaction Address Space | DRAM Space (DRAM) |
|---|---|---|
| TSEG (T) | (TOLUD – STOLEN – TSEG) to TOLUD – STOLEN | (TOLUD – STOLEN – TSEG) to TOLUD – STOLEN |
SMM and VGA Access Through GTT TLB
Accesses through GTT TLB address translation SMM DRAM space are not allowed. Writes will be routed to memory address 000C_0000h with byte enables de-asserted and reads will be routed to Memory address 000C_0000h. If a GTT TLB translated address hits VGA space, an error is recorded.
PCI Express* and DMI Interface originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation. If a GTT TLB translated address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface write accesses through the GMADR range will not be snooped. Only PCI Express and DMI assesses to GMADR linear range (defined using fence registers) are supported. PCI Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when translated, the resulting physical address is to enable SMM DRAM space, the request will be remapped to address 000C_0000h with de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported. Therefore, there are no address translation concerns. PCI Express and DMI Interface reads to GMADR will be remapped to address 000C_0000h. The read will complete with UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure fetch is not in SMM (actually, anything above base of TSEG or 640 KB - 1 MB). Thus, the fetches will be invalid and go to address 000C_0000h. This is not specific to PCI Express or DMI; it also applies to processor or Processor Graphics engines.
Intel Management Engine (Intel ME) Stolen Memory Accesses
There are two ways to validly access Intel® ME stolen memory:
- PCH accesses mapped to VCm will be decoded to ensure only Intel® ME stolen memory is targeted. These VCm accesses will route non-snooped directly to DRAM. This is the means by which the Intel® ME (located within the PCH) is able to access the Intel® ME stolen range.
- The display engine is allowed to access Intel® ME stolen memory as part of Intel® KVM technology flows. Specifically, display-initiated HHP reads (for displaying a Intel® KVM technology frame) and display initiated LP non-snoop writes (for display writing an Intel® KVM technology captured frame) to Intel® ME stolen memory are allowed.
I/O Address Space
The system agent generates either DMI Interface or PCI Express* bus cycles for all processor I/O accesses that it does not claim. The Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) are used to generate PCI configuration space access.
The processor allows 64K+3 bytes to be addressed within the I/O space. The upper 3 locations can be accessed only during I/O address wrap-around.
A set of I/O accesses are consumed by the Processor Graphics device if it is enabled. The mechanisms for Processor Graphics I/O decode and the associated control is explained in following sub-sections.
The I/O accesses are forwarded normally to the DMI Interface bus unless they fall within the PCI Express I/O address range as defined by the mechanisms explained below. I/O writes are NOT posted. Memory writes to PCH or PCI Express are posted. The PCI Express devices have a register that can disable the routing of I/O cycles to the PCI Express device.
The processor responds to I/O cycles initiated on PCI Express or DMI with an UR status. Upstream I/O cycles and configuration cycles should never occur. If one does occur, the transaction will complete with an UR completion status.
I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from the processor as one transaction. The reads will be split into two separate transactions. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries will be split into two transactions by the processor.
PCI Express* I/O Address Mapping
The processor can be programmed to direct non-memory (I/O) accesses to the PCI Express bus interface when processor initiated I/O cycle addresses are within the PCI Express I/O address range. This range is controlled using the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in Device 1 Functions 0, 1, 2 configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the purpose of address decoding, the device assumes that the lower 12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O address range alignment to a 4 KB boundary and produces a size granularity of 4 KB.
The processor positively decodes I/O accesses to PCI Express I/O address space as defined by the following equation:
I/O_Base_Address ≤ processor I/O Cycle Address ≤ I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of I/O space claimed by the PCI Express device.
The processor also forwards accesses to the Legacy VGA I/O ranges according to the settings in the PEG configuration registers BCTRL (VGA Enable) and PCICMD (IOAE), unless a second adapter (monochrome) is present on the DMI Interface/PCI (or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit. When MDAP is set to 1, the processor will decode legacy monochrome I/O ranges and forward them to the DMI Interface. The I/O ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh.
The PEG I/O address range registers defined above are used for all I/O space allocation for any devices requiring such a window on PCI-Express.
The PCICMD register can disable the routing of I/O cycles to PCI Express.
Direct Media Interface (DMI) Interface Decode Rules
All “SNOOP semantic” PCI Express* transactions are kept coherent with processor caches.
All “Snoop not required semantic” cycles reference the main DRAM address range. PCI Express non-snoop initiated cycles are not snooped.
The processor accepts accesses from the DMI Interface to the following address ranges:
- All snoop memory read and write accesses to Main DRAM including PAM region (except stolen memory ranges, TSEG, A0000h – BFFFFh space)
- Write accesses to enabled VGA range, MBASE/MLIMIT, and PMBASE/PMLIMIT will be routed as peer cycles to the PCI Express interface.
- Write accesses above the top of usable DRAM and below 4 GB (not decoding to PCI Express or GMADR space) will be treated as master aborts.
- Read accesses above the top of usable DRAM and below 4 GB (not decoding to PCI Express) will be treated as unsupported requests.
- Reads and accesses above the TOUUD will be treated as unsupported requests on VC0.
DMI Interface memory read accesses that fall between TOLUD and 4 GB are considered invalid and will master abort. These invalid read accesses will be reassigned to address 000C_0000h and dispatch to DRAM. Reads will return unsupported request completion. Writes targeting PCI Express space will be treated as peer-to-peer cycles.
There is a known usage model for peer writes from DMI to PEG. A video capture card can be plugged into the PCH PCI bus. The video capture card can send video capture data (writes) directly into the frame buffer on an external graphics card (writes to the PEG port). As a result, peer writes from DMI to PEG should be supported.
I/O cycles and configuration cycles are not supported in the upstream direction. The result will be an unsupported request completion status.
DMI Accesses to the Processor that Cross Device Boundaries
The processor does not support transactions that cross device boundaries. This should not occur because PCI Express transactions are not allowed to cross a 4 KB boundary.
For reads, the processor will provide separate completion status for each naturally-aligned 64-byte block or, if chaining is enabled, each 128-byte block. If the starting address of a transaction hits a valid address, the portion of a request that hits that target device (PCI Express or DRAM) will complete normally.
If the starting transaction address hits an invalid address, the entire transaction will be remapped to address 000C_0000h and dispatched to DRAM. A single unsupported request completion will result.
Traffic Class (TC) / Virtual Channel (VC) Mapping Details
- VC0 (enabled by default)
- Snoop port and Non-snoop Asynchronous transactions are supported.
- Internal Graphics GMADR writes can occur. These writes will NOT be snooped regardless of the snoop not required (SNR) bit.
- Processor Graphics GMADR reads (unsupported).
- Peer writes can occur. The SNR bit is ignored.
- MSI can occur. These will route and be sent to the cores as Intlogical/IntPhysical interrupts regardless of the SNR bit.
- VLW messages can occur. These will route and be sent to the cores as VLW messages regardless of the SNR bit.
- MCTP messages can occur. These are routed in a peer fashion.
- VC1 (Optionally enabled)
- Supports non-snoop transactions only. (Used for isochronous traffic). The PCI Express* Egress port (PXPEPBAR) should also be programmed appropriately.
- The snoop not required (SNR) bit should be set. Any transaction with the SNR bit not set will be treated as an unsupported request.
- MSI and peer transactions are treated as unsupported requests.
- No “pacer” arbitration or TWRR arbitration will occur. Never remaps to different port. (PCH takes care of Egress port remapping). The PCH meters TCm Intel® ME accesses and Intel® High Definition Audio (Intel® HD Audio) TC1 access bandwidth.
- Processor Graphics GMADR writes and GMADR reads are not supported.
- VCm accesses
- VCm access only map to Intel® ME stolen DRAM. These transactions carry the direct physical DRAM address (no redirection or remapping of any kind will occur). This is how the PCH Intel® ME accesses its dedicated DRAM stolen space.
- DMI block will decode these transactions to ensure only Intel® ME stolen memory is targeted, and abort otherwise.
- VCm transactions will only route non-snoop.
- VCm transactions will not go through VTd remap tables.
- The remapbase/remaplimit registers to not apply to VCm transactions.
Example: DMI Upstream VC0 Memory Map
PCI Express* Interface Decode Rules
All “SNOOP semantic” PCI Express* transactions are kept coherent with processor caches. All “Snoop not required semantic” cycles should reference the direct DRAM address range. PCI Express non-snoop initiated cycles are not snooped. If a “Snoop not required semantic” cycle is outside of the address range mapped to system memory, then it will proceed as follows:
- Reads: Sent to DRAM address 000C_0000h (non-snooped) and will return “unsuccessful completion”.
- Writes: Sent to DRAM address 000C_0000h (non-snooped) with byte enables all disabled Peer writes from PEG to DMI are not supported.
If PEG bus master enable is not set, all reads and writes are treated as unsupported requests.
TC/VC Mapping Details
- VC0 (enabled by default)
—Snoop port and Non-snoop Asynchronous transactions are supported.
- Processor Graphics GMADR writes can occur. Unlike FSB chipsets, these will NOT be snooped regardless of the snoop not required (SNR) bit.
- Processor Graphics GMADR reads (unsupported).
- Peer writes are only supported between PEG ports. PEG to DMI peer write accesses are NOT supported.
- MSI can occur. These will route to the cores (IntLogical/IntPhysical) regardless of the SNR bit.
- VC1 is not supported.
- VCm is not supported.
PEG Upstream VC0 Memory Map
Legacy VGA and I/O Range Decode Rules
The legacy 128 KB VGA memory range 000A_0000h – 000B_FFFFh can be mapped to Processor Graphics (Device 2), PCI Express (Device 1 Functions), and/or to the DMI interface depending on the programming of the VGA steering bits. Priority for VGA mapping is constant in that the processor always decodes internally mapped devices first. Internal to the processor, decode precedence is always given to Processor Graphics. The processor always positively decodes internally mapped devices, namely the Processor Graphics. Subsequent decoding of regions mapped to either PCI Express port or the DMI Interface depends on the Legacy VGA configurations bits (VGA Enable and MDAP).
For the remainder of this section, PCI Express can refer to either the device 1 port functions.
VGA range accesses will always be mapped as UC type memory.
Accesses to the VGA memory range are directed to Processor Graphics depend on the configuration. The configuration is specified by:
- Processor Graphics controller in Device 2 is enabled (DEVEN.D2EN bit 4)
- Processor Graphics VGA in Device 0 Function 0 is enabled through register GGC bit 1.
- Processor Graphics's memory accesses (PCICMD2 04h – 05h, MAE bit 1) in Device 2 configuration space are enabled.
- VGA compatibility memory accesses (VGA Miscellaneous Output register – MSR Register, bit 1) are enabled.
- Software sets the proper value for VGA Memory Map Mode register (VGA GR06 Register, bits 3:2). See the following table for translations.
| Memory Access GR06(3:2) | A0000h - AFFFFh | B0000h - B7FFFh MDA | B8000h - BFFFFh |
|---|---|---|---|
| 00 | Processor Graphics | Processor Graphics | Processor Graphics |
| 01 | Processor Graphics | PCI Express bridge or DMI interface | PCI Express bridge or DMI interface |
| 10 | PCI Express bridge or DMI interface | Processor Graphics | PCI Express bridge or DMI interface |
| 11 | PCI Express bridge or DMI interface | PCI Express bridge or DMI interface | Processor Graphics |
VGA I/O range is defined as addresses where A[15:0] are in the ranges 03B0h to 03BBh, and 03C0h to 03DFh. VGA I/O accesses are directed to Processor Graphics depends on the following configuration:
- Processor Graphics controller in Device 2 is enabled through register DEVEN.D2EN bit 4.
- Processor Graphics VGA in Device 0 Function 0 is enabled through register GGC bit 1.
- Processor Graphics's I/O accesses (PCICMD2 04 – 05h, IOAE bit 0) in Device 2 are enabled.
- VGA I/O decodes for Processor Graphics uses 16 address bits (15:0) there is no aliasing. This is different when compared to a bridge device (Device 1) that used only 10 address bits (A 9:0) for VGA I/O decode.
- VGA I/O input/output address select (VGA Miscellaneous Output register - MSR Register, bit 0) is used to select mapping of I/O access as defined in the following table.
| I/O Access MSRb0 | 3CX | 3DX | 3B0h – 3BBh | 3BCh – 3BFh |
|---|---|---|---|---|
| 0 | Processor Graphics | PCI Express bridge or DMI interface | Processor Graphics | PCI Express bridge or DMI interface |
| 1 | Processor Graphics | Processor Graphics | PCI Express bridge or DMI interface | PCI Express bridge or DMI interface |
For regions mapped outside of the Processor Graphics (or if Processor Graphics is disabled), the legacy VGA memory range A0000h – BFFFFh are mapped to the DMI Interface or PCI Express depending on the programming of the VGA Enable bit in the BCTRL configuration register in the PEG configuration space, and the MDAPxx bits in the Legacy Access Control (LAC) register in Device 0 configuration space. The same register controls mapping VGA I/O address ranges. The VGA I/O range is defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases – A[15:10] are not decoded). The function and interaction of these two bits is described below:
VGA Enable: Controls the routing of processor initiated transactions targeting VGA compatible I/O and memory address ranges. When this bit is set, the following processor accesses will be forwarded to the PCI Express:
- Memory accesses in the range 0A0000h to 0BFFFFh
- I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (including ISA address aliases – A[15:10] are not decoded)
When this bit is set to a “1”:
- Forwarding of these accesses issued by the processor is independent of the I/O address and memory address ranges defined by the previously defined base and limit registers.
- Forwarding of these accesses is also independent of the settings of the ISA Enable settings if this bit is “1”.
- Accesses to I/O address range x3BCh – x3BFh are forwarded to the DMI Interface.
When this bit is set to a “0”:
- Accesses to I/O address range x3BCh – x3BFh are treated like any other I/O accesses; the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and ISA enable bit is not set. Otherwise, these accesses are forwarded to the DMI interface.
- VGA compatible memory and I/O range accesses are not forwarded to PCI Express but rather they are mapped to the DMI Interface, unless they are mapped to PCI Express using I/O and memory range registers defined above (IOBASE, IOLIMIT)
The following table shows the behavior for all combinations of MDA and VGA.
| VGA_en | MDAP | Range | Destination | Exceptions / Notes |
|---|---|---|---|---|
| 0 | 0 | VGA, MDA | DMI interface | |
| 0 | 1 | Illegal | Undefined behavior results | |
| 1 | 0 | VGA | PCI Express | |
| 1 | 1 | VGA | PCI Express | |
| 1 | 1 | MDA | DMI interface | x3BCh – x3BEh will also go to DMI interface |
The same registers control mapping of VGA I/O address ranges. The VGA I/O range is defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases – A[15:10] are not decoded). The function and interaction of these two bits is described below.
MDA Present (MDAP): This bit works with the VGA Enable bit in the BCTRL register of Device 1 to control the routing of processor-initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is set, accesses to I/O address range x3BCh – x3BFh are forwarded to the DMI Interface. If the VGA enable bit is not set, accesses to I/O address range x3BCh – x3BFh are treated just like any other I/O accesses; that is, the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and the ISA enable bit is not set; otherwise, the accesses are forwarded to the DMI Interface. MDA resources are defined as the following:
| Range Type | Address |
|---|---|
| Memory | 0B0000h – 0B7FFFh |
| I/O | 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh (Including ISA address aliases, A[15:10] are not used in decode) |
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the DMI interface even if the reference includes I/O locations not listed above.
For I/O reads that are split into multiple DWord accesses, this decode applies to each DWord independently. For example, a read to x3B3h and x3B4h (quadword read to x3B0h with BE#=E7h) will result in a DWord read from PEG at 3B0h (BE#=Eh), and a DWord read from DMI at 3B4h (BE=7h). Since the processor will not issue I/O writes crossing the DWord boundary, this case does not exist for writes.
Summary of decode priority:
- Else, if MDA Present (if VGA on PEG is enabled), DMI gets:
- Else, if VGA on PEG is enabled, PEG gets:
- Else, if ISA Enable=1, DMI gets:
- Else, IOBASE/IOLIMIT apply.
I/O Mapped Registers
The processor contains two registers that reside in the processor I/O address space - the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.
Registers
Available registers for Meteor Lake are listed in the navigation.