12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
Base Address Register 1 (TBT_DMA_CFG_FIRST16DWORD_DW5_INST) – Offset 14
Contains BAR1 in 32 bit addressing and BAR0_HIGH in 64 bit addressing.
BAR0 is used for DMA Memory Access. BAR1 is used for MSIX Memory accessing.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:12 | 0x0 | RW | BAR is Read Write (BAR1_3) If 64 bit addressing: BAR0_HIGH[31:12]. Otherswise If 32 bit addressing and MSIX enabled: BAR1[31:12]: RW for MSIX BAR. Otherwise not used. |
11:4 | 0x0 | RO | BAR is Read Only (BAR1_2) If 64 bit addressing: BAR0_HIGH[11:4]. Otherwise If 32 bit addressing and MSIX is enabled: BAR1[11:4]: RO for MSIX BAR. Otherwise not used. |
3 | 0x0 | RO | BAR is Prefetchable (BAR1_1) Set to 1 if there are no side affects on reads; zero otherwise. |
2:0 | 0x0 | RO | Memory Space Indicator and Type (BAR1_0) If 64 bit addressing: BAR0_HIGH[2:0] otherwise If 32 bit addressing and MSIX enabled: BAR1[2:0]: 000b. Otherwise not used. |