12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
D13:F1 USB Device Controller (xDCI) Configuration Registers Registers
This chapter documents the registers in Bus 0, Device 13, Function 1.
USB Device Controller (xDCI).
Offset | Size (Bytes) | Register Name (Register Symbol) | Default Value |
---|---|---|---|
0h | 4 | 00000000h | |
4h | 4 | 00000000h | |
8h | 4 | 00000000h | |
Ch | 4 | Cache Line Size, Master Latency Timer, Header Type and BIST (CLLATHEADERBIST) | 00000000h |
10h | 4 | 00000000h | |
14h | 4 | 00000000h | |
18h | 4 | 00000000h | |
1Ch | 4 | 00000000h | |
2Ch | 4 | 00000000h | |
30h | 4 | 00000000h | |
34h | 4 | 00000000h | |
3Ch | 4 | 00000000h | |
80h | 4 | 00000000h | |
84h | 4 | Power Management Control And Status Register (PMECTRLSTATUS) | 00000000h |
90h | 4 | Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) | 00000000h |
94h | 4 | Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) | 00000000h |
98h | 4 | Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) | 00000000h |
9Ch | 4 | 00000000h | |
A0h | 4 | D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) | 00000000h |
F8h | 4 | 00000000h |