12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
VS CAP 12 Thunderbolt Access Through PCIE Command Register (TBT_DMA_CFG_VS_CAP_12) – Offset D4
VS CAP 12 PCIe Mailbox feature Thunderbolt access through PCIe Command register.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0x0 | RW | Time Out (TIMEOUT) Set by Hardware in case of timeout |
30 | 0x0 | RW | Command In Progress (COMMAND_IN_PROGRESS) Set by Software to start wr/rd command and cleared by Hardware when command is finished or timeouts |
29:24 | 0x0 | RW | RESERVED (RESERVED_29) Reserved |
23 | 0x0 | RW | CMD 2 (CMD_2) 0: Regular Target bus access |
22 | 0x0 | RW | CMD 1 (CMD_1) 0: Regular Target bus access |
21 | 0x0 | RW | CMD 0 (CMD_0) 0: Read |
20:19 | 0x0 | RW | Configuration Space (CS) Sets CS Target bus value:
|
18:13 | 0x0 | RW | Port ID (PORT) Sets Port# Target bus value |
12:0 | 0x0 | RW | DW Index (DW_INDEX) Sets DW Index Target bus value |