12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
Port X Hardware LPM Control Register (PORTHLPMC1) – Offset 48C
There are 9 PORTHLPMC registers at offsets 48Ch, 49Ch, 4ACh, 4BCh, 4CCh, 4DCh, 4ECh, 4FCh, 50Ch
This register is reset only by platform hardware during cold reset or in response to a Host Controller Reset (HCRST).
The definition for the fields depend on the protocol supported. For USB3 this register is reserved and shall be treated by software as RsvdP. For USB2 the definition is given below. Fields contain parameters neccessary for xHC to automatically generate an LPM Token to the downstream device.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:14 | 0x0 | RO | RESERVED (RSVD) RESERVED |
13:10 | 0x0 | RW | Host Initiated Resume Duration-Deep (HIRDD) System software sets this field to indicate to the recipient device how long the xHC will drive resume if an exit from L1. The HIRDD value is is encoded as follows: |
9:2 | 0x0 | RW/P | L1 Timeout (L1_TO) Timeout value for L1 inactivity timer. This field shall be set to 00h by assertion of PR to '1'. Following are permissible values: |
1:0 | 0x0 | RW/P | Host Initiated Resume Duration Mode (HIRDM) Indicates which HIRD value should be used. Following are permissible values: |