Link Control (LCTL_0_0_0_DMIBAR) – Offset 88
Allows control of PCI Express link.
Bit Range | Default | Access | Field Name and Description |
15:10 | 0h | RO | Reserved |
9 | 0x0 | RO | Hardware Autonomous Width Disable (HAWD) OPI: Not available When Set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to 0b. |
8 | 0h | RO | Reserved |
7 | 0x0 | RW | Extended Sync (ES) OPI: Not available 0: Standard Fast Training Sequence (FTS). 1: Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state. This mode provides external devices (e.g., logic analyzers) monitoring the Link time to achieve bit and symbol lock before the link enters L0 and resumes communication. This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns. |
6 | 0h | RO | Reserved |
5 | 0x0 | RO | Retrain Link (RL) 0: Normal operation. 1: Full Link retraining is initiated by directing the Physical Layer LTSSM from L0, L0s, or L1 states to the Recovery state. This bit always returns 0 when read. This bit is cleared automatically (no need to write a 0). |
4:2 | 0h | RO | Reserved |
1:0 | 0x0 | RO | Active State PM (ASPM) Controls the level of active state power management supported on the given link. 00: Disabled 01: L0s Entry Supported 10: L1 Entry Supported 11: L0s and L1 Entry Supported |