12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset A0
D0idle_Max_Power_On_Latency register set at boot and Power control enable register to enable communication with the PGCB block below the Bridge
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:22 | 0x0 | RO | Reserved (RESERVED0) Reserved |
21 | 0x0 | RW/P | Hardware Autonomous Enable (HAE) Hardware Autonomous Enable. |
20 | 0x0 | RO | Reserved (RESERVED1) Reserved |
19 | 0x1 | RW/P | Sleep Enable (SLEEP_EN) Sleep Enable |
18 | 0x0 | RW/P | D3-Hot Enable (D3HEN) If 1b then function will power gate when idle and the PMCSR[1:0] register in the function = 11b (D3). |
17 | 0x0 | RW/P | Device Idle Enable (DEVIDLEN) If 1b then the function will power gate when idle and the DevIdle register (DevIdleC[2] = 1) is set. |
16 | 0x0 | RW/P | PMC Request Enable (PMCRE) PMC Request Enable |
15:13 | 0x0 | RO | Reserved (RESERVED2) Reserved |
12:10 | 0x2 | RW/O/P | Power Latency Scale (POW_LAT_SCALE) Power On Latency Scale |
9:0 | 0x0 | RW/O/P | Power Latency Value (POW_LAT_VALUE) Power On Latency value |