12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 1) Registers
This chapter documents the DMIBAR registers.
Base address of these registers are defined in the DMIBAR_0_0_0_PCI register in Bus 0, Device 0, Function 0.
Offset | Size (Bytes) | Register Name (Register Symbol) | Default Value |
---|---|---|---|
0h | 4 | DMI Virtual Channel Enhanced Capability (DMIVCECH_0_0_0_DMIBAR) | 00000000h |
4h | 4 | DMI Port VC Capability Register 1 (DMIPVCCAP1_0_0_0_DMIBAR) | 00000000h |
8h | 4 | DMI Port VC Capability Register 2 (DMIPVCCAP2_0_0_0_DMIBAR) | 00000000h |
Ch | 2 | 0000h | |
10h | 4 | 00000000h | |
1Ch | 4 | 00000000h | |
26h | 2 | 0000h | |
34h | 4 | 00000000h | |
3Eh | 2 | 0000h | |
40h | 4 | DMI Root Complex Link Declaration (DMIRCLDECH_0_0_0_DMIBAR) | 00000000h |
44h | 4 | 00000000h | |
50h | 4 | 00000000h | |
5Ch | 4 | 00000000h | |
60h | 4 | 00000000h | |
68h | 4 | 00000000h | |
88h | 2 | 0000h | |
1C4h | 4 | 00000000h | |
1C8h | 4 | 00000000h | |
1CCh | 4 | DMI Uncorrectable Error Severity (DMIUESEV_0_0_0_DMIBAR) | 00000000h |
1D0h | 4 | 00000000h | |
1D4h | 4 | 00000000h |