Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) – Offset 10 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) – Offset 10

Bit Range	Default	Access	Field Name and Description
63:44	0h	RO	Reserved
43	0x0	RO/V	PASID Support Limitation (PSL) This field is valid only when Process Address Space ID Support (PASID) field (bit 40) is reported as Set. When this field is reported as Set, extendedcontext-entries with PASID Enable (PASIDE) field Set do not support Requests-withoutPASID. Hardware implementations must report a value of 0 in this field. Virtual implementations may report a value of 1 in this field to disallow guest software from using an extended-context-entry for both Virtual Address (VA) and I/O Virtual Address (IOVA) concurrently.
42	0x1	RO/V	Page Request Draining Support (PDS) 0: Hardware does not support Page-Request Drain (PD) flag in Inv_wait_dsc. 1: Hardware supports Page-Request Drain (PD) flag in Inv_wait_dsc. This field is valid only when Device-TLB support field is reported as Set.
41	0x1	RO/V	Device-TLB Invalidation Throttle (DIT) 0: Hardware does not support Device-TLB Invalidation Throttling. 1: Hardware supports Device-TLB Invalidation Throttling. This field is valid only when Page Request Support (PRS) field is reported as Set.
40	0x0	RO/V	Process Address Space ID Support (PASID) 0: Hardware does not support requests tagged with Process Address Space IDs. 1: Hardware supports requests tagged with Process Address Space IDs.
39:35	0x0	RO/V	PASID Size Supported (PSS) This field reports the PASID size supported by the remapping hardware for requests-with-PASID. A value of N in this field indicates hardware supports PASID field of N+1 bits (For example, value of 7 in this field, indicates 8-bit PASIDs are supported). Requests-with-PASID with PASID value beyond the limit specified by this field are treated as error by the remapping hardware. This field is valid only when PASID field is reported as Set.
34	0x0	RO/V	Extended Accessed Flag Support (EAFS) 0: Hardware does not support the extended-accessed (EA) bit in first-level paging-structure entries. 1: Hardware supports the extended accessed (EA) bit in first-level paging-structure entries. This field is valid only when PASID field is reported as Set.
33	0x0	RO/V	No Write Flag Support (NWFS) 0: Hardware ignores the No Write (NW) flag in Device-TLB translationrequests, and behaves as if NW is always 0. 1: Hardware supports the No Write (NW) flag in Device-TLB translationrequests. This field is valid only when Device-TLB support (DT) field is reported as Set.
32	0h	RO	Reserved
31	0x0	RO/V	Supervisor Request Support (SRS) 0: H/W does not support requests-with-PASID seeking supervisor privilege. 1: H/W supports requests-with-PASID seeking supervisor privilege. The field is valid only when PASID field is reported as Set.
30	0x0	RO/V	Execute Request Support (ERS) 0: H/W does not support requests-with-PASID seeking execute permission. 1: H/W supports requests-with-PASID seeking execute permission. This field is valid only when PASID field is reported as Set.
29	0x0	RO/V	Page Request Support (PRS) 0: Hardware does not support Page Requests. 1: Hardware supports Page Requests This field is valid only when Device-TLB (DT) field is reported as Set.
28	0h	RO	Reserved
27	0x0	RO/V	Deferred Invalidate Support (DIS) 0: Hardware does not support deferred invalidations of IOTLB and Device-TLB. 1: Hardware supports deferred invalidations of IOTLB and Device-TLB. This field is valid only when PASID field is reported as Set.
26	0x0	RO/V	Nested Translation Support (NEST) 0: Hardware does not support nested translations. 1: Hardware supports nested translations. This field is valid only when PASID field is reported as Set.
25	0x0	RO/V	Memory Type Support (MTS) 0: Hardware does not support Memory Type in first-level translation and Extended Memory type in second-level translation. 1: Hardware supports Memory Type in first-level translation and Extended Memory type in second-level translation. This field is valid only when PASID and ECS fields are reported as Set. Remapping hardware units with, one or more devices that operate in processor coherency domain, under its scope must report this field as Set.
24	0x0	RO/V	Extended Context Support (ECS) 0: Hardware does not support extended-root-entries and extended-context-entries. 1: Hardware supports extended-root-entries and extended-context-entries. Implementations reporting PASID or PRS fields as Set, must report this field as Set.
23:20	0xF	RO/V	Maximum Handle Mask Value (MHMV) The value in this field indicates the maximum supported value for the Handle Mask (HM) field in the interrupt entry cache invalidation descriptor (iec_inv_dsc). This field is valid only when the IR field in Extended Capability register is reported as Set.
19:18	0h	RO	Reserved
17:8	0x50	RO/V	IOTLB Register Offset (IRO) This field specifies the offset to the IOTLB registers relative to the register base address of this remapping hardware unit. If the register base address is X, and the value reported in this field is Y, the address for the first IOTLB invalidation register is calculated as X+(16*Y).
7	0x1	RO/V	Snoop Control (SC) 0: Hardware does not support 1-setting of the SNP field in the page-table entries. 1: Hardware supports the 1-setting of the SNP field in the page-table entries.
6	0x1	RO/V	Pass Through (PT) 0: Hardware does not support pass-through translation type in context entries and extended-context-entries. 1: Hardware supports pass-through translation type in context entries and extended-context-entries. Pass-through translation is specified through Translation-Type (T) field value of 10b in context-entries, or T field value of 010b in extended-context-entries. Hardware implementations supporting PASID must report a value of 1b in this field.
5	0h	RO	Reserved
4	0x1	RO/V	Extended Interrupt Mode (EIM) 0: On Intel64 platforms, hardware supports only 8-bit APIC-IDs (xAPIC mode). 1: On Intel64 platforms, hardware supports 32-bit APIC-IDs (x2APIC mode). This field is valid only on Intel64 platforms reporting Interrupt Remapping support (IR field Set).
3	0x1	RO/V	Interrupt Remapping support (IR) 0: Hardware does not support interrupt remapping. 1: Hardware supports interrupt remapping. Implementations reporting this field as Set must also support Queued Invalidation (QI).
2	0x0	RO/V	Device-TLB Support (DT) 0: Hardware does not support device-IOTLBs. 1: Hardware supports Device-IOTLBs. Implementations reporting this field as Set must also support Queued Invalidation (QI). Hardware implementations supporting I/O Page Requests (PRS field Set in Extended Capability register) must report a value of 1b in this field.
1	0x1	RO/V	Queued Invalidation Support (QI) 0: Hardware does not support queued invalidations. 1: Hardware supports queued invalidations.
0	0x0	RO/V	Page-Walk Coherency (C) This field indicates if hardware access to the root, context, extended-context and interrupt-remap tables, and second-level paging structures for requests-without-PASID, are coherent (snooped) or not. 0: Indicates hardware accesses to remapping structures are non-coherent. 1: Indicates hardware accesses to remapping structures are coherent. Hardware access to advanced fault log, invalidation queue, invalidation semaphore, page-request queue, PASID-table, PASID-state table, and first-level page-tables are always coherent.