12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767625 | 07/13/2023 | Public |
Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR) – Offset 70
Register to set up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled
This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register)
The alignment of the protected high memory region base depends on the number of reserved bits (N:0) of this register. Software may determine N by writing all 1s to this register, and finding most significant zero bit position below host address width (HAW) in the value read back from the register. Bits N:0 of this register are decoded by hardware as all 0s
Software may setup the protected high memory region either above or below 4GB
Software must not modify this register when protected memory regions are enabled (PRS field Set in PMEN_REG).
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
63:42 | 0h | RO | Reserved |
41:20 | 0x0 | RW | Protected High-Memory Base (PHMB) This register specifies the base of protected (high) memory region in system memory Hardware ignores, and does not implement, bits 63:HAW, where HAW is the host address width. |
19:0 | 0h | RO | Reserved |