600 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
ID
648364
Date
05/10/2022
Legal Disclaimer
Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
System Management
High Precision Event Timer (HPET)
PCH Thermal Sensor
Power Delivery
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface (eSPI)
General Purpose Input and Output
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Functional Description
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
DMA Controller
The UART controllers 0 and 1 (UART0 and UART1) have an integrated DMA controller. Each channel contains a 64-byte FIFO. Max. burst size supported is 32 bytes.
UART controller 2 (UART2) only implements the host controllers and does not incorporate a DMA. Therefore, UART2 is restricted to operate in PIO mode only.
DMA Transfer and Setup Modes
The DMA can operate in the following modes:
- Memory to peripheral transfers. This mode requires that the peripheral control the flow of the data to itself.
- Peripheral to memory transfer. This mode requires that the peripheral control the flow of the data from itself.
The DMA supports the following modes for programming:
- Direct programming. Direct register writes to DMA registers to configure and initiate the transfer.
- Descriptor based linked list. The descriptors will be stored in memory (such as DDR or SRAM). The DMA will be informed with the location information of the descriptor. DMA initiates reads and programs its own register. The descriptors can form a linked list for multiple blocks to be programmed.
- Scatter Gather mode
Channel Control
- The source transfer width and destination transfer width are programmable. It can vary to 1 byte, 2 bytes, and 4 bytes.
- Burst size is configurable per channel for source and destination. The number is a power of 2 and can vary between 1,2,4,...,128. this number times the transaction width gives the number of bytes that will be transferred per burst.
- Individual Channel enables. If the channel is not being used, then it should be clock gated.
- Programmable Block size and Packing/Unpacking. Block size of the transfer is programmable in bytes. the block size is not be limited by the source or destination transfer widths.
- Address incrementing modes: The DMA has a configurable mechanism for computing the source and destination addresses for the next transfer within the current block. The DMA supports incrementing addresses and constant addresses.
- Flexibility to configure any hardware handshake sideband interface to any of the DMA channels.
- Early termination of a transfer on a particular channel.