Pin Straps

600 Series Chipset Family Platform Controller Hub

Datasheet, Volume 1 of 2

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ID 648364

Date 05/10/2022

Version

The following signals are used for static configuration. They are sampled at the rising edge of either DSW_PWROK, RSMRST#, or PCH_PWROK to select configuration and then revert later to their normal usage. To invoke the associated mode, the signal should meet both set up time of 1 us and hold time of 65 us, with respect to the rising edge of the sampling signal.

The PCH implements soft straps, which are used to configure specific functions within the PCH and processor very early in the boot process before BIOS or software intervention. The PCH will read soft strap data out of the SPI device prior to the de-assertion of reset to both the Intel^® Management Engine and the Host system.

Pin Straps

Signal	Usage	When Sampled	Comment
GPP_B14 / SPKR	Top Swap Override	Rising edge of PCH_PWROK	The strap has a 20 kohm ± 30% internal pull-down. 0=>Disable “Top Swap” mode. (Default) 1=>Enable “Top Swap” mode. This inverts an address on access to SPI, so the alternate boot block is fetched instead of the original boot-block. The PCH will invert the appropriate address lines (A[23:16]) as selected in Top Swap Block size soft strap. Notes: The internal pull-down is disabled after PCH_PWROK is high. Software will not be able to clear the Top Swap bit until the system is rebooted. The status of this strap is readable using the Top Swap bit (Bus0, Device31, Function0, offset DCh, bit4). This signal is in the primary well.
GPP_I18 / GSPI0_MOSI	No Reboot	Rising edge of PCH_PWROK	The strap has a 20 kohm ± 30% internal pull-down. 0=>Disable “No Reboot” mode. (Default) 1=>Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP. Notes: The internal pull-down is disabled after PCH_PWROK is high. This signal is in the primary well.
GPP_C2 / SMBALERT#	TLS Confidentiality	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0=>Disable Intel^® CSME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). (Default) 1=>Enable Intel^® CSME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel^® AMT with TLS. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_C5 / SML0ALERT#	eSPI Disable	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0 = Enable eSPI. (Default) 1 = Disable eSPI. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
SPI0_MOSI	Reserved	Rising edge of RSMRST#	External pull-up is required. Recommend 4.7 kohm pull-up. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.
GPP_B23 / SML1ALERT# / PCHHOT#	XTAL Frequency Selection Bit 1	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This is bit 1 (MSB) of the 2-bit encoded pin straps for XTAL Frequency Selection. This strap is used in conjunction with XTAL Frequency Selection Bit 0 on GPP_J2 / CNV_BRI_DT / UART0_RTS# pin. 2-bit XTAL Frequency Selection encodings: 00 = 24 MHz (default) 01 = Reserved 10 = 38.4 MHz 11 = 25 MHz Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
SPI0_IO2	Reserved	Rising edge of RSMRST#	External pull-up is required. Recommend 100 kohm if pulled up to 3.3 V or 75 kohm if pulled up to 1.8 V. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.
SPI0_IO3	Reserved	Rising edge of RSMRST#	External pull-up is required. Recommend 100 kohm if pulled up to 3.3 V or 75 kohm if pulled up to 1.8 V. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.
GPP_R2 / HDA_SDO / HDACPU_SDO	Reserved	Rising edge of PCH_PWROK	This strap has a 20 kohm ± 30% internal pull-down. 0=> Enable security measures defined in the Flash Descriptor. (Default) 1=> Disable Flash Descriptor Security (override). This strap should only be asserted high using external Pull-up in manufacturing/debug environments ONLY. Notes: The internal pull-down is disabled after PCH_PWROK is high. This signal is in the primary well.
GPP_H12 / SML2ALERT#	eSPI Flash Sharing Mode	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0=>Master Attached Flash Sharing (MAFS) enabled (Default) 1=>Slave Attached Flash Sharing (SAFS) enabled. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_H15 / SML3ALERT#	JTAG ODT Disable	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0=> JTAG ODT is disabled (default) 1=> JTAG ODT is enabled Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_H18 / SML4ALERT#	VCCSPI Voltage Configuration	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0=> VCCSPI at 3.3 V (Default) 1=> VCCSPI at 1.8 V Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
DBG_PMODE	Reserved	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-up. This strap should sample high. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-up is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPD7	Reserved	Rising edge of DSW_PWROK	This strap has a 20 kohm ± 30% internal pull-down. This strap should sample LOW. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-down is disabled after DSW_PWROK is high. This signal is in the DSW well.
GPP_J2 / CNV_BRI_DT / UART0_RTS#	XTAL Frequency Selection Bit 0	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This is bit 0 (LSB) of the 2-bit encoded pin straps XTAL Frequency Selection . This strap is used in conjunction with XTAL Frequency Selection Bit 1 on GPP_B23 / SML1ALERT# / PCHHOT# pin. 2-bit XTAL Frequency Selection encodings: 00 = 24 MHz (default) 01 = Reserved 10 = 38.4 MHz 11 = 25 MHz Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_J4 / CNV_RGI_DT / UART0_TXD	M.2 CNVi Mode Select	Rising edge of RSMRST#	This strap does not have an internal pull-up or pull-down. A weak external pull-up is required. 0=>Integrated CNVi enabled. 1=>Integrated CNVi disabled. Note:When a RF companion chip is connected to the PCH CNVi interface, the device internal pull-down resistor will pull the strap low to enable CNVi interface.
GPP_I22 /GSPI1_MOSI	Boot BIOS Strap (BBS)	Rising edge of PCH_PWROK	This signal has a 20 kohm ± 30% internal pull-down. 0=>BIOS fetches are routed to SPI (MAF) or the eSPI Flash Channel (SAF) 1=>BIOS fetches are routed to the eSPI Peripheral Channel Notes: The internal pull-down is disabled after PCH_PWROK de-asserts. This signal is in the primary well.