- Driven High during S0 and driven Low during S0i3 when all criteria for assertion are met.
- SLP_S4# is driven low in S4/S5.
- SLP_S5# is driven high in S4, driven low in S5.
- In non-Deep Sx mode, pin is driven low.
- Based on wake events and Intel® CSME state. SUSPWRDNACK is always ‘0’ while in M0 or M3, but can be driven to ‘0’ or ‘1’ while in Moff state. SUSPWRDNACK is the default mode of operation. If Deep Sx is supported, then subsequent boots will default to SUSWARN#.
- The pin requires glitch-free output sequence. The pad should only be pulled low momentarily when the corresponding buffer power supply is not stable.
- Based on wake event and Intel CSME state.
- Pull-down is configurable and can be enabled in Deep Sx state; refer to DSX_CFG register for more details.
- When platform enters Deep Sx, the SLP_S4# and SLP_S5# pin will retain the value it held prior to Deep Sx entry.
- Internal weak pull-down resistor is enabled during power sequencing.
- NA
- Pin state is a function of whether the platform is configured to have Intel CSME on or off in Sx.
- Output High-Z, not glitch free.
- Output High-Z, glitch free with ~120 k Pull-down during respective power sequencing
- Output High-Z, not glitch free.
- Output High-Z, glitch free with ~20 k Pull-down during respective power sequencing.
- Reset reference for primary well pins is RSMRST#, DSW well pins is DSW_PWROK, and RTC well pins is RTCRST#.
- Sx can be optionally be high when RSMRST# is high and the buffer moves to its native mode at which point it will become low.
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