GPIO fixed functions (Signals for Integrated Connectivity (CNVi) and Discrete Connectivity (CNVd) functions

GPP_​D5 / CNV_​RF_​RESET#

I/O

For CNVi: RF companion (CRF) reset signal, active low. Require a 75 kohm Pull-Down on platform/motherboard level. It is recommended not to use it for bootstrapping during early Platform init flows.

For discrete connectivity with UART host support: Optional Bluetooth* I²S bus sync

GPP_​J2 / CNV_​BRI_​DT / UART0_​RTS#

O

For CNVi: BRI bus TX.

For discrete connectivity with UART host support: Bluetooth* UART RTS#

GPP_​J3 / CNV_​BRI_​RSP / UART0_​RXD

I

For CNVi: BRI bus RX.

For discrete connectivity with UART host support: Bluetooth* UART RXD

GPP_​J4 / CNV_​RGI_​DT / UART0_​TXD

O

For CNVi: RGI bus TX. RGI_​DT is used by the platform to strap presence of the CRF. Requires weak pull up of 20Kohm on the platform.

For discrete connectivity with UART host support: Bluetooth* UART TXD

GPP_​J5 / CNV_​RGI_​RSP / UART0_​CTS#

I

For CNVi: RGI bus RX.

For discrete connectivity with UART host support: Bluetooth* UART CTS#

GPP_​J0 / CNV_​PA_​BLANKING

I/O

For CNVi and discrete connectivity : Optional WLAN/Bluetooth* WWAN co-existence signal. Used to be co-existence signal for external GNSS solution

I

For CNVi and discrete connectivity: Optional WLAN/Bluetooth* WWAN co-existence signal (Input)

O

For CNVi and discrete connectivity : Optional WLAN/Bluetooth* WWAN co-existence signal (Output)

Fixed special purpose I/O

CNV_​WT_​CLKP

O

CNVio bus TX CLK+

CNV_​WT_​CLKN

O

CNVio bus TX CLK-

CNV_​WT_​D0P

O

CNVio bus Lane 0 TX+

CNV_​WT_​D0N

O

CNVio bus Lane 0 TX-

CNV_​WT_​D1P

O

CNVio bus Lane 1 TX+

CNV_​WT_​D1N

O

CNVio bus Lane 1 TX-

CNV_​WR_​CLKP

I

CNVio bus RX CLK+

CNV_​WR_​CLKN

I

CNVio bus RX CLK-

CNV_​WR_​D0P

I

CNVio bus Lane 0 RX+

CNV_​WR_​D0N

I

CNVio bus Lane 0 RX-

CNV_​WR_​D1P

I

CNVio bus Lane 1 RX+

CNV_​WR_​D1N

I

CNVio bus Lane 1 RX-

Selectable special purpose I/O

USB2P_​14

I/O

Bluetooth* USB host bus (positive) for discrete connectivity. Optional to connect to a Bluetooth* USB+ pin on the Bluetooth* module. Port 14 is the recommended port but other USB 2.0 ports can be selected for this function.

USB2N_​14

I/O

Bluetooth* USB host bus (negative) for discrete connectivity. Optional to connect to a Bluetooth* USB+ pin on the Bluetooth* module. Port 14 is the recommended port but other USB 2.0 ports can be selected for this function.

PCIE12_​TXP

O

Wi-Fi* PCIe* host bus TX (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PERp0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

PCIE12_​TXN

O

Wi-Fi* PCIe* host bus TX (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PERn0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

PCIE12_​RXP

I

Wi-Fi* PCIe* host bus RX (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PETp0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

PCIE12_​RXN

I

Wi-Fi* PCIe* host bus RX (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PETn0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

CLKOUT_​PCIE_​P3

O

Wi-Fi* PCIe* host bus clock (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* REFCLKp pin on the Wi-Fi* module. This is the recommended clock signal but other PCIe* clocks can be selected for this function.

CLKOUT_​PCIE_​N3

O

Wi-Fi* PCIe* host bus clock (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* REFCLKp pin on the Wi-Fi* module. This is the recommended clock signal but other PCIe* clocks can be selected for this function.

CL_​RST#

O

Wi-Fi* CLINK host bus reset for discrete connectivity with CLINK support (Intel^® vPro™). Optional to connect to a Wi-Fi* CLINK reset pin on the Intel^® vPro™ Wi-Fi* module.

CL_​DATA

I/O

Wi-Fi* CLINK host bus data for discrete connectivity with CLINK support (Intel^® vPro™). Optional to connect to a Wi-Fi* CLINK data pin on the Intel^® vPro™ Wi-Fi* module.

CL_​CLK

O

Wi-Fi* CLINK host bus clock for discrete connectivity with CLINK support (Intel^® vPro™). Optional to connect to a Wi-Fi* CLINK clock pin on the Intel^® vPro™ Wi-Fi* module.

W_​Disable1# (GPIO)

O

Used for Wi-Fi* RF-Kill control.

This pin can be connected to a platform switch or to SoC GPIOs (recommendation- if possible do not use GPIOs that have Platform impact as “bootstraps” during platform init).

The signal must keep value in Sx state (configured in BIOS)

The W_​Disable signal have a Pull-up embedded in the CRF silicon, (this is an Active-Low signal).

W_​Disable2# (GPIO)

O

Used for Bluetooth* RF-Kill control.

This pin can be connected to a platform switch or to SoC GPIOs (recommendation- if possible do not use GPIOs that have Platform impact as “bootstraps” during platform init).

The signal must keep value in Sx state (configured in BIOS)

The W_​Disable signal have a Pull-up embedded in the CRF silicon, (this is an Active-Low signal).