600 Series Chipset Family Platform Controller Hub

Datasheet, Volume 1 of 2

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ID 648364
Date 05/10/2022
Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction PCH Controller Device IDs Memory Mapping System Management High Precision Event Timer (HPET) PCH Thermal Sensor Power Delivery Pin Straps Electrical and Thermal Characteristics Ballout Definition 8254 Timers Audio Voice and Speech Controller Link Processor Sideband Signals Digital Display Signals Enhanced Serial Peripheral Interface (eSPI) General Purpose Input and Output Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Gigabit Ethernet Controller Integrated Sensor Hub (ISH) PCH and System Clocks PCI Express* (PCIe*) Power Management Real Time Clock (RTC) Serial ATA (SATA) System Management Interface and SMLink Host System Management Bus (SMBus) Controller Serial Peripheral Interface (SPI) Intel® Serial IO Generic SPI (GSPI) Controllers Testability Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Universal Serial Bus (USB) Connectivity Integrated (CNVi) GPIO Serial Expander Direct Media Interface Private Configuration Space Target Port ID Miscellaneous Signals
Legal Disclaimer
Revision History
Introduction
Introduction Overview PCH SKUs Flexible High Speed I/O
Overview
PCH SKUs
Flexible High Speed I/O
Flexible High Speed I/O Intel® 600 Series Chipset Family PCH Flexible I/O Lane Selection
Intel® 600 Series Chipset Family PCH
Flexible I/O Lane Selection
PCH Controller Device IDs
Device and Revision ID
Device and Revision ID
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
Functional Description PCI Devices and Functions Fixed I/O Address Ranges Variable I/O Decode Ranges
PCI Devices and Functions
Fixed I/O Address Ranges
Variable I/O Decode Ranges
Memory Map
Memory Map Boot Block Update Scheme
Boot Block Update Scheme
System Management
System Management Theory of Operation
Theory of Operation
Theory of Operation Handling an Intruder TCO Modes
Handling an Intruder
TCO Modes
High Precision Event Timer (HPET)
Feature Overview
Feature Overview
Feature Overview Timer Accuracy Timer Off-load Interrupt Mapping Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels
Timer Accuracy
Timer Off-load
Interrupt Mapping
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
PCH Thermal Sensor
PCH Thermal Sensor Modes of Operation Temperature Trip Point Thermal Sensor Accuracy (Taccuracy) Thermal Reporting to an EC Thermal Trip Signal (PCHHOT#)
Modes of Operation
Temperature Trip Point
Thermal Sensor Accuracy (Taccuracy)
Thermal Reporting to an EC
Thermal Trip Signal (PCHHOT#)
Power Delivery
Power Delivery Power and Ground Signals
Power and Ground Signals
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
8254 Timers Timer Programming Reading from the Interval Timer
Timer Programming
Reading from the Interval Timer
Audio Voice and Speech
Audio Voice and Speech Feature Overview Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Feature Overview
Feature Overview Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities Intel® High Definition Audio Interface Capabilities Direct Attached Digital Microphone (PDM) Interface USB Audio Offload Support Intel® Display Audio Interface MIPI® SoundWire* Interface
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Controller Link
Controller Link Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States External CL_RST# Pin Driven/Open-drained Mode Support
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
External CL_RST# Pin Driven/Open-drained Mode Support
Processor Sideband Signals
Processor Sideband Signals Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Digital Display Signals
Digital Display Signals Signal Description Embedded DisplayPort* (eDP*) Backlight Control Signals Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Embedded DisplayPort* (eDP*) Backlight Control Signals
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Operating Frequency Protocols WAIT States from eSPI Slave In-Band Link Reset Slave Discovery Flash Sharing Mode PECI Over eSPI Multiple OOB Master Channels and Supported Transactions
Operating Frequency
Protocols
WAIT States from eSPI Slave
In-Band Link Reset
Slave Discovery
Flash Sharing Mode
PECI Over eSPI
Multiple OOB Master
Channels and Supported Transactions
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
General Purpose Input and Output
General Purpose Input and Output Signal Description Functional Description
Signal Description
Functional Description
Functional Description Configurable GPIO Voltage GPIO Buffer Impedance Compensation Interrupt / IRQ via GPIO Requirement Programmable Hardware Debouncer Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO GPIO Blink (BK) and Serial Blink (SBK) GPIO Ownership Native Function and TERM Bit Setting
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Power Management Interrupts Error Handling Programmable SDA Hold Time
Protocols Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Programmable SDA Hold Time
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Gigabit Ethernet Controller
Gigabit Ethernet Controller Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description GbE PCI Express* Bus Interface Error Events and Error Reporting Ethernet Interface PCI Power Management
GbE PCI Express* Bus Interface
Error Events and Error Reporting
Ethernet Interface
PCI Power Management
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH) Functional Description Feature Overview Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description ISH Micro-Controller SRAM PCI Host Interface Power Domains and Management ISH IPC ISH Interrupt Handling via IOAPIC (Interrupt Controller)
ISH Micro-Controller
SRAM
PCI Host Interface
Power Domains and Management
ISH IPC
ISH Interrupt Handling via IOAPIC (Interrupt Controller)
Feature Overview
Feature Overview ISH I2C Controllers ISH UART Controller ISH GSPI Controller ISH GPIOs
ISH I2C Controllers
ISH UART Controller
ISH GSPI Controller
ISH GPIOs
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
PCH and System Clocks
PCH and System Clocks ICC I/O Signal Pin States
ICC
ICC Signal Description
Signal Description
I/O Signal Pin States
PCI Express* (PCIe*)
PCI Express* (PCIe*) Functional Description Signal Description PCI Express* Port Support Feature Details
Functional Description
Functional Description Interrupt Generation PCI Express* Power Management Dynamic Link Throttling Port 8xh Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single - Root I/O Virtualization (SR - IOV) SERR# Generation Hot - Plug PCI Express* Lane Polarity Inversion Precision Time Measurement (PTM)
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
PCI Express* Port Support Feature Details
Power Management
Power Management Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Features Power Management States PCH and System Power States SMI#/SCI Generation C-States Sleep States Event Input Signals and Their Usage ALT Access Mode System Power Supplies, Planes, and Signals Legacy Power Management Theory of Operation Reset Behavior
Features
Power Management States
PCH and System Power States
SMI#/SCI Generation
C-States
Sleep States
Event Input Signals and Their Usage
ALT Access Mode
System Power Supplies, Planes, and Signals
Legacy Power Management Theory of Operation
Reset Behavior
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Serial ATA (SATA)
Serial ATA (SATA) Functional Description Signals Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description SATA 6 Gb/s Support SATA Feature Support Hot - Plug Operation Intel® Rapid Storage Technology (Intel® RST) Power Management Operation SATA Device Presence SATA LED Advanced Host Controller Interface (AHCI) Operation Enclosure Management (SGPIO Signals)
SATA 6 Gb/s Support
SATA Feature Support
Hot - Plug Operation
Intel® Rapid Storage Technology (Intel® RST)
Power Management Operation
SATA Device Presence
SATA LED
Advanced Host Controller Interface (AHCI) Operation
Enclosure Management (SGPIO Signals)
Signals Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
System Management Interface and SMLink
System Management Interface and SMLink Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Integrated USB-C Usage
Integrated USB-C Usage
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Host System Management Bus (SMBus) Controller
Host System Management Bus (SMBus) Controller Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States SMBus Power Gating
Functional Description
Functional Description Host Controller SMBus Slave Interface
Host Controller
SMBus Slave Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
SMBus Power Gating
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States VCCSPI Voltage (3.3 V or 1.8 V) Selection
Functional Description
Functional Description SPI0 for Flash SPI0 Support for TPM
SPI0 for Flash
SPI0 Support for TPM
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
VCCSPI Voltage (3.3 V or 1.8 V) Selection
Intel® Serial IO Generic SPI (GSPI) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Testability
Testability Intel® Trace Hub (Intel® TH) Direct Connect Interface (DCI) JTAG Boundry Scan Sideband Signals
Intel® Trace Hub (Intel® TH)
Direct Connect Interface (DCI)
Direct Connect Interface (DCI) Out Of Band (OOB) Hosting DCI USB 3.2 Hosting DCI.DBC Platform Setup
Out Of Band (OOB) Hosting DCI
USB 3.2 Hosting DCI.DBC
Platform Setup
JTAG
JTAG Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Boundry Scan Sideband Signals
Boundry Scan Sideband Signals Signal Description
Signal Description
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Universal Serial Bus (USB)
Universal Serial Bus (USB) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Supported USB 2.0 Ports
Functional Description
Functional Description eXtensible Host Controller Interface (xHCI) Controller USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
eXtensible Host Controller Interface (xHCI) Controller
USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Supported USB 2.0 Ports
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Functional Description Signal Description Integrated Pull-ups and Pull-downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
I/O Signal Planes and States
GPIO Serial Expander
GPIO Serial Expander Functional Description Signal Description Integrated Pull-ups and Pull-downs
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
Direct Media Interface
Direct Media Interface Functional Description Signal Description I/O Signal Planes and States
Functional Description
Functional Description Lane Reversal Polarity Inversion
Lane Reversal
Polarity Inversion
Signal Description
I/O Signal Planes and States
Private Configuration Space Target Port ID
Miscellaneous Signals
Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Legal Disclaimer
Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
System Management
High Precision Event Timer (HPET)
PCH Thermal Sensor
Power Delivery
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface (eSPI)
General Purpose Input and Output
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals

Lane Reversal

x4 and x8 DMI PCH Lane Reversal is supported. OEM can enable this feature in PCH to ease the DMI link routing (between CPU and PCH) on the board. PCH DMI Lane Reversal is enabled or disabled through a SoftStrap.

Polarity Inversion