600 Series Chipset Family Platform Controller Hub

Datasheet, Volume 1 of 2

ID 648364
Date 05/10/2022
Document Table of Contents

Signal Description

Signal Descriptions

Name Type Description
Intel High Definition Audio Signals
GPP_​R4 / HDA_​RST# O Intel HD Audio Reset: Master H/W reset to internal/external codecs.
GPP_​R1 / HDA_​SYNC O Intel HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. Also used to encode the stream number.
GPP_​R0 / HDA_​BCLK / HDACPU_​BCLK O Intel HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel HD Audio controller.
GPP_​R2 / HDA_​SDO / HDACPU_​SDO O Intel HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s.
GPP_​R3 / HDA_​SDI0 / HDACPU_​SDI I Intel HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered.
GPP_​R5 / HDA_​SDI1 I Intel HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered.
Intel Display Audio Interface
HDACPU_​BCLK

or

GPP_​R0 / HDA_​BCLK / HDACPU_​BCLK

O Display Audio Bit Clock: Serial data clock generated by the Intel HD Audio controller. PCH supports data rate of up to 96 Mb/s.
HDACPU_​SDO

or

GPP_​R2 / HDA_​SDO / HDACPU_​SDO

O Display Audio Serial Data Out: Serial TDM data output to the codec. PCH supports data rate of up to 96 Mb/s.
HDACPU_​SDI

or

GPP_​R3 / HDA_​SDI0 / HDACPU_​SDI

I Display Audio Serial Data In: Serial TDM data input from the codec. PCH supports data rate of up to 96 Mb/s.
DMIC Interface
GPP_​S6 / SNDW4_​CLK / DMIC_​CLKA0 O Digital Mic Clock A0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control.
GPP_​S4 / SNDW3_​CLK / DMIC_​CLKA1 O Digital Mic Clock A1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control.
GPP_​S2 / SNDW2_​CLK / DMIC_​CLKB0 O Digital Mic Clock B0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control.
GPP_​S3 / SNDW2_​DATA / DMIC_​CLKB1 O Digital Mic Clock B1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control.
GPP_​S7 / SNDW4_​DATA / DMIC_​DATA0 I Digital Mic Data:Serial data input from the digital mic.
GPP_​S5 / SNDW3_​DATA / DMIC_​DATA1 I Digital Mic Data:Serial data input from the digital mic.
SoundWire Interface
GPP_​S0 / SNDW1_​CLK I/O SoundWire Clock: Serial data clock to external peripheral devices.
GPP_​S1 / SNDW1_​DATA I/O SoundWire Data: Serial data input from external peripheral devices.
GPP_​S2 / SNDW2_​CLK / DMIC_​CLKB0 I/O SoundWire Clock: Serial data clock to external peripheral devices.
GPP_​S3 / SNDW2_​DATA / DMIC_​CLKB1 I/O SoundWire Data: Serial data input from external peripheral devices.
GPP_​S4 / SNDW3_​CLK / DMIC_​CLKA1 I/O SoundWire Clock: Serial data clock to external peripheral devices.
GPP_​S5 / SNDW3_​DATA / DMIC_​DATA1 I/O SoundWire Data: Serial data input from external peripheral devices.
GPP_​S6 / SNDW4_​CLK / DMIC_​CLKA0 I/O SoundWire Clock: Serial data clock to external peripheral devices.
GPP_​S7 / SNDW4_​DATA / DMIC_​DATA0 I/O SoundWire Data: Serial data input from external peripheral devices.
SNDW_​RCOMP I/O SoundWire RCOMP:200ohm +/- 1% compensation resistor required to ground.
Misc
GPP_​B14 / SPKR O Speaker Output:Used for connection to external speaker for POST sounds if not using HD_​Audio embedded option.