| GPP_E4 / SATA_DEVSLP0 | OD | Serial ATA Port [0] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. This pin can be mapped to SATA Port 0. |
| GPP_E5 / SATA_DEVSLP1 | OD | Serial ATA Port [1] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to Pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. This pin can be mapped to SATA Port 1. |
| GPP_E6 / SATA_DEVSLP2 | OD | Serial ATA Port [2] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. This pin can be mapped to SATA Port 2. |
| GPP_F5 / SATA_DEVSLP3 | OD | Serial ATA Port [3] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. This pin can be mapped to SATA Port 3. |
| GPP_F6 / SATA_DEVSLP4 | OD | Serial ATA Port [4] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. This pin can be mapped to SATA Port 4. |
| GPP_F7 / SATA_DEVSLP5 | OD | Serial ATA Port [5] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. This pin can be mapped to SATA Port 5. |
| GPP_F8 / SATA_DEVSLP6 | OD | Serial ATA Port [6] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. - This pin can be mapped to SATA Port 6.
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| GPP_F9 / SATA_DEVSLP7 | OD | Serial ATA Port [7] Device Sleep: This is an open-drain pin on the PCH side. PCH will tri- state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up that's internal to the SATA device, per DEVSLP specification). PCH will drive pin low to signal an exit from DEVSLP state. - This pin can be mapped to SATA Port 7.
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| PCIE13_TXN / SATA0_TXN PCIE13_TXP / SATA0_TXP | O | Serial ATA Differential Transmit Pair 0: These outbound SATA Port 0 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE13_RXN / SATA0_RXN PCIE13_RXP / SATA0_RXP | I | Serial ATA Differential Receive Pair 0: These inbound SATA Port 0 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE14_TXN / SATA1_TXN PCIE14_TXP / SATA1_TXP | O | Serial ATA Differential Transmit Pair 1 :These outbound SATA Port 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE14_RXN / SATA1_RXN PCIE14_RXP / SATA1_RXP | I | Serial ATA Differential Receive Pair 1: These inbound SATA Port 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE15_TXN / SATA2_TXN PCIE15_TXP / SATA2_TXP | O | Serial ATA Differential Transmit Pair 2: These outbound SATA Port 2 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE15_RXN / SATA2_RXN PCIE15_RXP / SATA2_RXP | I | Serial ATA Differential Receive Pair 2: These inbound SATA Port 2 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE16_TXN / SATA3_TXN PCIE16_TXP / SATA3_TXP | O | Serial ATA Differential Transmit Pair 3: These outbound SATA Port 3 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE16_RXN / SATA3_RXN PCIE16_RXP / SATA3_RXP | I | Serial ATA Differential Receive Pair 3: These inbound SATA Port 3 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE17_TXN / SATA4_TXN PCIE17_TXP / SATA4_TXP | O | Serial ATA Differential Transmit Pair 4: These outbound SATA Port 4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE17_RXN / SATA4_RXN PCIE17_RXP / SATA4_RXP | I | Serial ATA Differential Receive Pair 4: These inbound SATA Port 4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE18_TXN / SATA5_TXN PCIE18_TXP / SATA5_TXP | O | Serial ATA Differential Transmit Pair 5: These outbound SATA Port 5 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE18_RXN / SATA5_RXN PCIE18_RXP / SATA5_RXP | I | Serial ATA Differential Receive Pair 5: These inbound SATA Port 5 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE19_TXN / SATA6_TXN PCIE19_TXP / SATA6_TXP | O | Serial ATA Differential Transmit Pair 6: These outbound SATA Port 6 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE19_RXN / SATA6_RXN PCIE19_RXP / SATA6_RXP | I | Serial ATA Differential Receive Pair 6: These inbound SATA Port 6 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE20_TXN / SATA7_TXN PCIE20_TXP / SATA7_TXP | O | Serial ATA Differential Transmit Pair 7: These outbound SATA Port 7 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| PCIE20_RXN / SATA7_RXN PCIE20_RXP / SATA7_RXP | I | Serial ATA Differential Receive Pair 7: These inbound SATA Port 7 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s. |
| GPP_E0 / SATAXPCIE0 / SATAGP0 | I | Serial ATA Port [0] General Purpose Inputs: When configured as SATAGP0, this is an input pin that is used as an interlock switch status indicator for SATA Port 0. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. The default use of this pin is GPP_E0. Pin defaults to Native mode as SATAXPCIE0 depends on soft-strap. |
| GPP_E1 / SATAXPCIE1 / SATAGP1 | I | Serial ATA Port [1] General Purpose Inputs: When configured as SATAGP1, this is an input pin that is used as an interlock switch status indicator for SATA Port 1. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. This default use of this pin is GPP_E1. Pin defaults to Native mode as SATAXPCIE1 depends on soft-strap. |
| GPP_E2 / SATAXPCIE2 / SATAGP2 | I | Serial ATA Port [2] General Purpose Inputs: When configured as SATAGP3, this is an input pin that is used as an interlock switch status indicator for SATA Port 3. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. The default use of this pin is GPP_E2. Pin defaults to Native mode as SATAXPCIE3 depends on soft-strap. |
| GPP_F0 / SATAXPCIE3 / SATAGP3 | I | Serial ATA Port [3] General Purpose Inputs: When configured as SATAGP3, this is an input pin that is used as an interlock switch status indicator for SATA Port 3. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. The default use of this pin is GPP_F0. Pin defaults to Native mode as SATAXPCIE3 depends on soft-strap. |
| GPP_F1 / SATAXPCIE4 / SATAGP4 | I | Serial ATA Port [4] General Purpose Inputs: When configured as SATAGP4, this is an input pin that is used as an interlock switch status indicator for SATA Port 4. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. The default use of this pin is GPP_F1. Pin defaults to Native mode as SATAXPCIE4 depends on soft-strap. |
| GPP_F2 / SATAXPCIE5 / SATAGP5 | I | Serial ATA Port [5] General Purpose Inputs: When configured as SATAGP5, this is an input pin that is used as an interlock switch status indicator for SATA Port 5. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. The default use of this pin is GPP_F2. Pin defaults to Native mode as SATAXPCIE5 depends on soft-strap. |
| GPP_F3 / SATAXPCIE6 / SATAGP6 | I | Serial ATA Port [6] General Purpose Inputs: When configured as SATAGP6, this is an input pin that is used as an interlock switch status indicator for SATA Port 6. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. - The default use of this pin is GPP_F3. Pin defaults to Native mode as SATAXPCIE6 depends on soft-strap.
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| GPP_F4 / SATAXPCIE7 / SATAGP7 | I | Serial ATA Port [7] General Purpose Inputs: When configured as SATAGP7, this is an input pin that is used as an interlock switch status indicator for SATA Port 7. Drive the pin to '0' to indicate that the switch is closed and to '1' to indicate that the switch is open. - The default use of this pin is GPP_F4. Pin defaults to Native mode as SATAXPCIE7 depends on soft-strap.
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| GPP_E8 / SATALED# / SPI1_CS1# | OD | Serial ATA LED: This signal is an open-drain output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external Pull-up resistor to VCC3_3 is required. |
| GPP_F10 / SATA_SCLOCK | OD | SGPIO Reference Clock: The SATA controller uses rising edges of this clock to transmit serial data, and the target uses the falling edge of this clock to latch data. The SClock frequency supported is 32 kHz. If SGPIO interface is not used, this signal can be used as GPP_F10. |
| GPP_F11 / SATA_SLOAD | OD | SGPIO Load: The controller drives a '1' at the rising edge of SCLOCK to indicate either the start or end of a bit stream. A 4-bit vendor specific pattern will be transmitted right after the signal assertion. If SGPIO interface is not used, this signal can be used as GPP_F11. |
| GPP_F13 / SATA_SDATAOUT0 | OD | SGPIO Dataout0: Driven by the controller to indicate the drive status in the following sequence: drive 0, 1,2, 3, 4, 5, 6, 7, 0, 1, 2… If SGPIO interface is not used, the signals can be used as GPP_F13. |
| GPP_F12 / SATA_SDATAOUT1 | OD | SGPIO Dataout1: Driven by the controller to indicate the drive status in the following sequence: drive 0, 1,2, 3, 4, 5, 6, 7, 0, 1, 2… If SGPIO interface is not used, the signals can be used as GPP_F12. |