Intel® 600 Series Chipset Family PCH

North PGS = North Flex HSIO PCH Section Covering PCIe/GbE/SATA

South PD = South Flex HSIO PCH Section Covering PCIe/DMI

South U = South Flex HSIO PCH Section Covering USB 3.2

LR = Lane Reversal

“Not Available” = The identified PHY Lane and its associated Flex I/O Lane are not available for any High Speed I/O (HSIO) Interface within the selected Configuration Option

The 46 Flexible HSIO Lanes on Intel^® 600 Series Chipset Family PCH support the following configurations:

1. Up to 28 PCIe* Lanes with a maximum of 12 PCIe* Gen4 Lanes
   • A maximum of sixteen PCIe* Root Ports (or devices) can be enabled
     • When a GbE Port is enabled, the maximum number of PCIe* Root Ports (or devices) that can be enabled reduces based off the following:

       --> Max PCIe* Root Ports (or devices) = 16 - GbE (0 or 1)

2. Up to eight SATA Lanes (Lanes 0-3 and 4-7)
   • A maximum of eight SATA Ports (or devices) can be enabled.
3. Up to ten USB 3.2 Gen 1x1/2x1 Lanes
   • A maximum of ten USB 3.2 Gen 1x1/2x1 Ports can be enabled
   • USB 3.2 Gen 1x1 = 5 GT\s
   • USB 3.2 Gen 2x1 = 10 GT\s
4. Up to eight USB 3.2 Gen 2x2 Lanes
   • A maximum of four USB 3.2 Gen 2x2 Ports can be enabled
   • USB 3.2  Gen 2x2 = 20 GT\s
5. Up to eight DMI Lanes for x4 and x8 support
6. Up to three GbE Lanes
   • A maximum of one GbE Port can be enabled